初始化毕业设计项目
This commit is contained in:
+44
@@ -0,0 +1,44 @@
|
||||
# Local IDE and assistant state
|
||||
.claude/
|
||||
.vscode/
|
||||
.qt_git_backup/
|
||||
|
||||
# Build outputs
|
||||
Objects/
|
||||
Listings/
|
||||
QT/build/
|
||||
QT/dist/
|
||||
QT/.qtcreator/
|
||||
|
||||
# Generated binaries and intermediates
|
||||
*.o
|
||||
*.obj
|
||||
*.d
|
||||
*.crf
|
||||
*.axf
|
||||
*.elf
|
||||
*.bin
|
||||
*.hex
|
||||
*.map
|
||||
*.lnp
|
||||
*.htm
|
||||
*.build_log.htm
|
||||
*.exe
|
||||
*.dll
|
||||
*.pdb
|
||||
|
||||
# Runtime data
|
||||
attendance.db
|
||||
attendance.log
|
||||
faces/
|
||||
|
||||
# OS/editor files
|
||||
.DS_Store
|
||||
Thumbs.db
|
||||
desktop.ini
|
||||
*.tmp
|
||||
*.bak
|
||||
*.swp
|
||||
*~
|
||||
__pycache__/
|
||||
*.pyc
|
||||
+89
@@ -0,0 +1,89 @@
|
||||
好的，这张图片详细说明了DS1302实时时钟（RTC）模块的工作原理、读写时序和寄存器定义。下面我将分部分进行文字描述。
|
||||
|
||||
### 1. 总体概述
|
||||
这张图片是DS1302芯片的技术资料片段，主要包含两部分：
|
||||
* **读/写时序图 (Timing Diagram)**：展示了微控制器如何通过三线串行接口与DS1302进行单字节的读取和写入操作。
|
||||
* **寄存器地址/定义表 (Register Map)**：列出了存储时间、日期等信息的各个寄存器的地址、位定义和取值范围。
|
||||
|
||||
---
|
||||
|
||||
### 2. 工作原理与读/写时序
|
||||
|
||||
这部分解释了DS1302的通信协议。
|
||||
|
||||
**核心通信方式：**
|
||||
|
||||
* **三线串行接口**：DS1302使用三根信号线与微控制器（如单片机）通信：
|
||||
1. **RST (Reset/Enable)**：复位/使能引脚。当RST为高电平时，DS1302被使能，可以进行通信。通信结束后，RST应恢复为低电平。
|
||||
2. **SCLK (Serial Clock)**：串行时钟引脚。由微控制器产生，用于同步数据的传输，在每个时钟脉冲的**上升沿**采样数据。
|
||||
3. **I/O (Input/Output)**：双向数据引脚。数据的输入和输出都通过这根线完成。
|
||||
|
||||
* **数据格式**：时间、日期数据均采用**BCD码 (Binary-Cododed Decimal)** 格式存储。简单来说，一个字节（8位）的高4位表示十位上的数字，低4位表示个位上的数字。例如，数字59在BCD码中表示为 `0101 1001`。
|
||||
|
||||
**时序图详解：**
|
||||
|
||||
#### a. SINGLE BYTE READ (单字节读取)
|
||||
|
||||
此过程用于从DS1302的某个寄存器中读取一个字节的数据。
|
||||
1. **启动通信**：微控制器将 **RST** 引脚拉高，使能DS1302。
|
||||
2. **发送命令字节**：微控制器通过 **I/O** 线发送一个8位的命令字节。这个命令字节在8个 **SCLK** 时钟脉冲的驱动下逐位传输。
|
||||
* 命令字节的格式为 `R/W A0 A1 A2 A3 A4 R/C 1`。
|
||||
* **R/W (Bit 7)**：读写控制位。对于读取操作，该位必须为 **1**。
|
||||
* **A0-A4 (Bit 1-5)**：寄存器地址位。
|
||||
* **R/C (Bit 6)**：寄存器类型选择位。选择时钟/日历寄存器或RAM寄存器。
|
||||
* **Bit 0**：必须为 **1**。
|
||||
* 综合来看，一个读取命令的地址字节，其最高位和最低位都必须是1。例如，读取秒寄存器（地址81h）的命令字节是 `1000 0001`。
|
||||
3. **接收数据字节**：在发送完命令字节后的接下来8个 **SCLK** 时钟脉冲期间，DS1302会通过 **I/O** 线将其寻址寄存器中的数据逐位发送给微控制器。此时，I/O线的控制权从微控制器转移到DS1302。
|
||||
4. **结束通信**：数据接收完毕后，微控制器将 **RST** 引脚拉低，结束本次通信。
|
||||
|
||||
#### b. SINGLE BYTE WRITE (单字节写入)
|
||||
|
||||
此过程用于向DS1302的某个寄存器写入一个字节的数据。
|
||||
1. **启动通信**：微控制器将 **RST** 引脚拉高。
|
||||
2. **发送命令字节**：微控制器通过 **I/O** 线发送一个8位的命令字节。
|
||||
* **R/W (Bit 7)**：读写控制位。对于写入操作，该位必须为 **0**。
|
||||
* 其余地址位（A0-A4, R/C）用于选择要写入的目标寄存器。
|
||||
* **Bit 0**：必须为 **0**。
|
||||
* 综合来看，一个写入命令的地址字节，其最高位和最低位都必须是0。例如，写入秒寄存器（地址80h）的命令字节是 `1000 0000`。
|
||||
3. **发送数据字节**：在发送完命令字节后的接下来8个 **SCLK** 时钟脉冲期间，微控制器继续通过 **I/O** 线将要写入的数据（D0-D7）逐位发送给DS1302。
|
||||
4. **结束通信**：数据发送完毕后，微控制器将 **RST** 引脚拉低，结束本次通信。
|
||||
|
||||
---
|
||||
|
||||
### 3. 寄存器地址/定义
|
||||
|
||||
这张表详细定义了DS1302内部各个寄存器的功能。
|
||||
|
||||
* **READ / WRITE**：分别列出了读取和写入某个功能寄存器时需要使用的十六进制地址。可以看出，同一功能的写地址通常是读地址减1（例如秒寄存器：读地址`81h`，写地址`80h`）。这实际上是因为命令字节的最低位（Bit 0）不同。
|
||||
* **BIT 7 - BIT 0**：描述了一个字节内每一位（或某几位）的含义。
|
||||
* **RANGE**：表示该寄存器存储数值的有效范围。
|
||||
|
||||
**主要寄存器解析：**
|
||||
|
||||
* **秒 (Seconds, 80h/81h)**：
|
||||
* `BIT 7`: **CH (Clock Halt)**。当此位为1时，时钟振荡器停止工作，时钟暂停，可以降低功耗。设为0时正常工作。
|
||||
* `BIT 6-4`: 秒的十位 (10 Seconds)。
|
||||
* `BIT 3-0`: 秒的个位 (Seconds)。
|
||||
* 范围：00-59。
|
||||
|
||||
* **分 (Minutes, 82h/83h)**:
|
||||
* `BIT 6-4`: 分的十位 (10 Minutes)。
|
||||
* `BIT 3-0`: 分的个位 (Minutes)。
|
||||
* 范围：00-59。
|
||||
|
||||
* **时 (Hour, 84h/85h)**：
|
||||
* `BIT 7`: **12/24** 模式选择。为1时是12小时制，为0时是24小时制。
|
||||
* **12小时制下**：`BIT 5` 为 **AM/PM** 标志（1=PM, 0=AM），`BIT 4` 是小时的十位，`BIT 3-0` 是小时的个位。
|
||||
* **24小时制下**：`BIT 5-4` 是小时的十位，`BIT 3-0` 是小时的个位。
|
||||
* 范围：1-12 (12小时制) 或 0-23 (24小时制)。
|
||||
|
||||
* **日 (Date, 86h/87h)** / **月 (Month, 88h/89h)** / **星期 (Day, 8Ah/8Bh)** / **年 (Year, 8Ch/8Dh)**：这些寄存器同样采用BCD码格式存储对应的日期信息。
|
||||
|
||||
* **写保护 (Write Protect, 8Eh/8Fh)**:
|
||||
* `BIT 7`: **WP (Write Protect)**。当此位为1时，所有时间、日期寄存器被保护，无法写入，防止数据被意外修改。要更新时间，必须先将此位清零。
|
||||
|
||||
* **涓流充电 (Trickle Charge, 90h/91h)**：此寄存器用于配置对备用电池或超级电容的涓流充电功能，图中只列出了其地址，具体位定义不完整。
|
||||
|
||||
**总结**，这张图是DS1302芯片的核心使用说明，它清晰地定义了如何通过一个精确的时序协议来读写芯片内的寄存器，从而实现对实时时钟的设置和读取。
|
||||
|
||||
|
||||
@@ -0,0 +1,97 @@
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
// <h> Debug MCU Configuration
|
||||
// <o0.0> DBG_SLEEP
|
||||
// <i> Debug Sleep Mode
|
||||
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||
// <o0.1> DBG_STOP
|
||||
// <i> Debug Stop Mode
|
||||
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||
// <o0.2> DBG_STANDBY
|
||||
// <i> Debug Standby Mode
|
||||
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||
// <o0.8> DBG_IWDG_STOP
|
||||
// <i> Debug independent watchdog stopped when core is halted
|
||||
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||
// <o0.9> DBG_WWDG_STOP
|
||||
// <i> Debug window watchdog stopped when core is halted
|
||||
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||
// <o0.10> DBG_TIM1_STOP
|
||||
// <i> Timer 1 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||
// <o0.11> DBG_TIM2_STOP
|
||||
// <i> Timer 2 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||
// <o0.12> DBG_TIM3_STOP
|
||||
// <i> Timer 3 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||
// <o0.13> DBG_TIM4_STOP
|
||||
// <i> Timer 4 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||
// <o0.14> DBG_CAN1_STOP
|
||||
// <i> Debug CAN1 stopped when Core is halted
|
||||
// <i> 0: Same behavior as in normal mode
|
||||
// <i> 1: CAN1 receive registers are frozen
|
||||
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||
// <i> 0: Same behavior as in normal mode
|
||||
// <i> 1: The SMBUS timeout is frozen
|
||||
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||
// <i> 0: Same behavior as in normal mode
|
||||
// <i> 1: The SMBUS timeout is frozen
|
||||
// <o0.17> DBG_TIM8_STOP
|
||||
// <i> Timer 8 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.18> DBG_TIM5_STOP
|
||||
// <i> Timer 5 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.19> DBG_TIM6_STOP
|
||||
// <i> Timer 6 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.20> DBG_TIM7_STOP
|
||||
// <i> Timer 7 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.21> DBG_CAN2_STOP
|
||||
// <i> Debug CAN2 stopped when Core is halted
|
||||
// <i> 0: Same behavior as in normal mode
|
||||
// <i> 1: CAN2 receive registers are frozen
|
||||
// <o0.25> DBG_TIM12_STOP
|
||||
// <i> Timer 12 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.26> DBG_TIM13_STOP
|
||||
// <i> Timer 13 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.27> DBG_TIM14_STOP
|
||||
// <i> Timer 14 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.28> DBG_TIM9_STOP
|
||||
// <i> Timer 9 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.29> DBG_TIM10_STOP
|
||||
// <i> Timer 10 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.30> DBG_TIM11_STOP
|
||||
// <i> Timer 11 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// </h>
|
||||
DbgMCU_CR = 0x00000007;
|
||||
// <<< end of configuration section >>>
|
||||
@@ -0,0 +1,9 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
|
||||
|
||||
<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
|
||||
<events>
|
||||
</events>
|
||||
|
||||
</component_viewer>
|
||||
@@ -0,0 +1,703 @@
|
||||
#include "Attendance.h"
|
||||
#include "Delay.h"
|
||||
#include "Debug.h"
|
||||
#include "esp8266.h" // ✨ 添加ESP8266头文件
|
||||
#include <string.h>
|
||||
#include <stdlib.h> // ← 添加atoi函数声明
|
||||
|
||||
// 配置参数
|
||||
#define MAX_ATTENDANCE_RECORDS 100 // 最大记录数量
|
||||
#define MIN_CONFIDENCE_THRESHOLD 0.75 // 最小置信度阈值
|
||||
#define MAX_TIME_SLOT_COUNT 10 // 最大时间段数量
|
||||
#define MAX_CACHED_IDS 50 // 最大缓存学号数量（从服务器下载）
|
||||
|
||||
// 时间段配置（动态从服务器更新）
|
||||
static TimeSlot time_slots[MAX_TIME_SLOT_COUNT];
|
||||
static uint8_t time_slot_count = 0; // 当前有效时间段数量
|
||||
|
||||
// 今日已签到学号缓存（从服务器下载）
|
||||
static char cached_student_ids[MAX_CACHED_IDS][20];
|
||||
static uint8_t cached_id_count = 0;
|
||||
|
||||
// 默认时间段配置（在服务器配置下载失败时使用）
|
||||
static const TimeSlot default_time_slots[] = {
|
||||
{1, 8, 0, 9, 30, "Morning Check-in"}, // 上午签到 08:00-09:30
|
||||
{1, 12, 0, 13, 0, "Noon Check-out"}, // 中午签退 12:00-13:00
|
||||
{1, 14, 0, 15, 0, "Afternoon Check-in"}, // 下午签到 14:00-15:00
|
||||
{1, 17, 0, 18, 30, "Evening Check-out"}, // 晚上签退 17:00-18:30
|
||||
};
|
||||
#define DEFAULT_TIME_SLOT_COUNT 4
|
||||
|
||||
// 当前时间（由外部更新，如果有RTC则从RTC读取）
|
||||
static uint8_t current_hour = 8;
|
||||
static uint8_t current_minute = 30;
|
||||
|
||||
// 内部存储
|
||||
static AttendanceRecord attendance_records[MAX_ATTENDANCE_RECORDS];
|
||||
static uint16_t record_count = 0;
|
||||
static uint32_t total_attendance_count = 0; // 总考勤人次
|
||||
|
||||
/**
|
||||
* @brief 初始化考勤模块
|
||||
*/
|
||||
void Attendance_Init(void)
|
||||
{
|
||||
record_count = 0;
|
||||
total_attendance_count = 0;
|
||||
current_hour = 8;
|
||||
current_minute = 0;
|
||||
memset(attendance_records, 0, sizeof(attendance_records));
|
||||
|
||||
// 初始化为默认时间段配置
|
||||
memcpy(time_slots, default_time_slots, sizeof(default_time_slots));
|
||||
time_slot_count = DEFAULT_TIME_SLOT_COUNT;
|
||||
|
||||
// 清空缓存
|
||||
cached_id_count = 0;
|
||||
memset(cached_student_ids, 0, sizeof(cached_student_ids));
|
||||
|
||||
DEBUG_INFO("[Attendance] Initialized with time slot mode");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 清空今日签到缓存
|
||||
*/
|
||||
void Attendance_ClearCache(void)
|
||||
{
|
||||
cached_id_count = 0;
|
||||
memset(cached_student_ids, 0, sizeof(cached_student_ids));
|
||||
DEBUG_INFO("[Attendance] Cache cleared");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 添加学号到缓存
|
||||
*/
|
||||
void Attendance_AddToCache(const char* student_id)
|
||||
{
|
||||
if (cached_id_count >= MAX_CACHED_IDS) {
|
||||
DEBUG_ERROR("[Attendance] Cache full, cannot add more IDs");
|
||||
return;
|
||||
}
|
||||
|
||||
// 检查是否已存在
|
||||
for (uint8_t i = 0; i < cached_id_count; i++) {
|
||||
if (strcmp(cached_student_ids[i], student_id) == 0) {
|
||||
return; // 已存在，不重复添加
|
||||
}
|
||||
}
|
||||
|
||||
strncpy(cached_student_ids[cached_id_count], student_id, 19);
|
||||
cached_student_ids[cached_id_count][19] = '\0';
|
||||
cached_id_count++;
|
||||
|
||||
DEBUG_PRINT("[Attendance] Added to cache: %s (total: %d)\r\n", student_id, cached_id_count);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 在本地缓存中查重
|
||||
* @retval 1=在缓存中找到（重复）, 0=未找到
|
||||
*/
|
||||
uint8_t Attendance_IsDuplicateInCache(const char* student_id)
|
||||
{
|
||||
for (uint8_t i = 0; i < cached_id_count; i++) {
|
||||
if (strcmp(cached_student_ids[i], student_id) == 0) {
|
||||
DEBUG_PRINT("[Attendance] Found in cache: %s\r\n", student_id);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 从服务器加载今日已签到记录到缓存
|
||||
* @retval 加载的记录数量
|
||||
*/
|
||||
uint8_t Attendance_LoadTodayRecordsFromServer(void)
|
||||
{
|
||||
char slot_start[8];
|
||||
char slot_end[8];
|
||||
char records_buffer[512];
|
||||
|
||||
// 获取当前时段时间
|
||||
Attendance_GetCurrentSlotTime(slot_start, slot_end);
|
||||
|
||||
DEBUG_PRINT("[Attendance] Loading today's records for slot %s-%s\r\n", slot_start, slot_end);
|
||||
|
||||
// 清空旧缓存
|
||||
Attendance_ClearCache();
|
||||
|
||||
// 从服务器下载
|
||||
uint8_t count = ESP8266_DownloadTodayRecords(slot_start, slot_end, records_buffer, sizeof(records_buffer));
|
||||
|
||||
if (count == 0) {
|
||||
DEBUG_INFO("[Attendance] No records to load or download failed");
|
||||
return 0;
|
||||
}
|
||||
|
||||
// 解析学号列表 (格式: "1","2","3")
|
||||
char* ptr = records_buffer;
|
||||
char student_id[20];
|
||||
uint8_t loaded = 0;
|
||||
|
||||
while (*ptr != '\0' && loaded < MAX_CACHED_IDS) {
|
||||
// 跳过引号和逗号
|
||||
while (*ptr == '"' || *ptr == ',' || *ptr == ' ') ptr++;
|
||||
|
||||
if (*ptr == '\0') break;
|
||||
|
||||
// 提取学号
|
||||
char* id_start = ptr;
|
||||
while (*ptr != '"' && *ptr != ',' && *ptr != '\0') ptr++;
|
||||
|
||||
uint8_t len = ptr - id_start;
|
||||
if (len > 0 && len < 20) {
|
||||
strncpy(student_id, id_start, len);
|
||||
student_id[len] = '\0';
|
||||
Attendance_AddToCache(student_id);
|
||||
loaded++;
|
||||
}
|
||||
}
|
||||
|
||||
DEBUG_PRINT("[Attendance] Loaded %d records from server\r\n", loaded);
|
||||
return loaded;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 更新时间段配置（从服务器下载后调用）
|
||||
* @param slots 新的时间段配置数组
|
||||
* @param count 时间段数量
|
||||
*/
|
||||
void Attendance_UpdateTimeSlots(TimeSlot* slots, uint8_t count)
|
||||
{
|
||||
if (count > MAX_TIME_SLOT_COUNT) {
|
||||
DEBUG_PRINT("[Attendance] Too many time slots: %d (max: %d)\r\n", count, MAX_TIME_SLOT_COUNT);
|
||||
return;
|
||||
}
|
||||
|
||||
// 更新时间段配置
|
||||
memcpy(time_slots, slots, count * sizeof(TimeSlot));
|
||||
time_slot_count = count;
|
||||
|
||||
DEBUG_PRINT("[Attendance] Time slots updated: %d slots loaded\r\n", count);
|
||||
|
||||
// 调试：打印所有时间段
|
||||
for (uint8_t i = 0; i < time_slot_count; i++) {
|
||||
DEBUG_PRINT("[Attendance] Slot %d: %s (%02d:%02d-%02d:%02d) %s\r\n",
|
||||
i, time_slots[i].name,
|
||||
time_slots[i].start_hour, time_slots[i].start_minute,
|
||||
time_slots[i].end_hour, time_slots[i].end_minute,
|
||||
time_slots[i].enabled ? "ENABLED" : "DISABLED");
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 从JSON字符串解析时间段配置
|
||||
* @param json_str JSON字符串（格式：{"time_slots":[{"enabled":true,"start_time":"08:00",...}]}）
|
||||
* @retval 成功解析的时间段数量
|
||||
*/
|
||||
uint8_t Attendance_ParseTimeSlotsJSON(const char* json_str)
|
||||
{
|
||||
TimeSlot temp_slots[MAX_TIME_SLOT_COUNT];
|
||||
uint8_t slot_count = 0;
|
||||
|
||||
DEBUG_INFO("[Attendance] Parsing time slots JSON...");
|
||||
DEBUG_PRINT("[Attendance] JSON: %s\r\n", json_str);
|
||||
|
||||
// 查找 "time_slots" 数组
|
||||
const char* ptr = strstr(json_str, "\"time_slots\"");
|
||||
if (ptr == NULL) {
|
||||
DEBUG_ERROR("[Attendance] Invalid JSON: no 'time_slots' field found");
|
||||
return 0;
|
||||
}
|
||||
|
||||
// 查找数组开始 '['
|
||||
ptr = strchr(ptr, '[');
|
||||
if (ptr == NULL) {
|
||||
DEBUG_ERROR("[Attendance] Invalid JSON: no '[' found");
|
||||
return 0;
|
||||
}
|
||||
ptr++; // 跳过 '['
|
||||
|
||||
while (*ptr == ' ' || *ptr == '\n' || *ptr == '\r' || *ptr == '\t') ptr++;
|
||||
if (*ptr == ']') {
|
||||
DEBUG_INFO("[Attendance] Empty time slot config, keeping current slots");
|
||||
return time_slot_count;
|
||||
}
|
||||
|
||||
// 解析每个时间段对象
|
||||
while (*ptr != '\0' && *ptr != ']' && slot_count < MAX_TIME_SLOT_COUNT)
|
||||
{
|
||||
// 跳过空格、换行、逗号
|
||||
while (*ptr == ' ' || *ptr == ',' || *ptr == '\n' || *ptr == '\r' || *ptr == '\t') ptr++;
|
||||
|
||||
// 查找对象开始
|
||||
if (*ptr != '{') break;
|
||||
ptr++; // 跳过 '{'
|
||||
|
||||
// 初始化当前时间段
|
||||
temp_slots[slot_count].enabled = 1;
|
||||
temp_slots[slot_count].start_hour = 0;
|
||||
temp_slots[slot_count].start_minute = 0;
|
||||
temp_slots[slot_count].end_hour = 0;
|
||||
temp_slots[slot_count].end_minute = 0;
|
||||
strcpy(temp_slots[slot_count].name, "Unknown");
|
||||
|
||||
// 解析对象字段
|
||||
while (*ptr != '\0' && *ptr != '}')
|
||||
{
|
||||
// 跳过空格、换行、逗号
|
||||
while (*ptr == ' ' || *ptr == ',' || *ptr == '\n' || *ptr == '\r' || *ptr == '\t') ptr++;
|
||||
|
||||
// 跳过引号
|
||||
if (*ptr == '"') ptr++;
|
||||
|
||||
// 解析字段名
|
||||
if (strncmp(ptr, "enabled", 7) == 0) {
|
||||
ptr = strchr(ptr, ':');
|
||||
if (ptr) {
|
||||
ptr++;
|
||||
while (*ptr == ' ') ptr++;
|
||||
// 处理 true/false 或 1/0
|
||||
temp_slots[slot_count].enabled = (*ptr == 't' || *ptr == '1') ? 1 : 0;
|
||||
}
|
||||
}
|
||||
else if (strncmp(ptr, "start_time", 10) == 0) {
|
||||
// 格式: "start_time": "08:30"
|
||||
ptr = strchr(ptr, ':');
|
||||
if (ptr) {
|
||||
ptr++;
|
||||
while (*ptr == ' ' || *ptr == '"') ptr++;
|
||||
// 解析 "HH:MM"
|
||||
temp_slots[slot_count].start_hour = (ptr[0] - '0') * 10 + (ptr[1] - '0');
|
||||
temp_slots[slot_count].start_minute = (ptr[3] - '0') * 10 + (ptr[4] - '0');
|
||||
}
|
||||
}
|
||||
else if (strncmp(ptr, "end_time", 8) == 0) {
|
||||
// 格式: "end_time": "09:30"
|
||||
ptr = strchr(ptr, ':');
|
||||
if (ptr) {
|
||||
ptr++;
|
||||
while (*ptr == ' ' || *ptr == '"') ptr++;
|
||||
// 解析 "HH:MM"
|
||||
temp_slots[slot_count].end_hour = (ptr[0] - '0') * 10 + (ptr[1] - '0');
|
||||
temp_slots[slot_count].end_minute = (ptr[3] - '0') * 10 + (ptr[4] - '0');
|
||||
}
|
||||
}
|
||||
else if (strncmp(ptr, "name", 4) == 0) {
|
||||
ptr = strchr(ptr, ':');
|
||||
if (ptr) {
|
||||
ptr++;
|
||||
while (*ptr == ' ' || *ptr == '"') ptr++;
|
||||
// 提取名称（直到遇到引号）
|
||||
const char* name_start = ptr;
|
||||
while (*ptr != '"' && *ptr != '\0') ptr++;
|
||||
int len = ptr - name_start;
|
||||
if (len > 19) len = 19;
|
||||
strncpy(temp_slots[slot_count].name, name_start, len);
|
||||
temp_slots[slot_count].name[len] = '\0';
|
||||
}
|
||||
}
|
||||
|
||||
// 移动到下一个字段或对象结束
|
||||
while (*ptr != '\0' && *ptr != ',' && *ptr != '}') ptr++;
|
||||
if (*ptr == ',') ptr++;
|
||||
}
|
||||
|
||||
if (*ptr == '}') ptr++; // 跳过 '}'
|
||||
|
||||
DEBUG_PRINT("[Attendance] Parsed slot %d: %s (%02d:%02d-%02d:%02d) %s\r\n",
|
||||
slot_count, temp_slots[slot_count].name,
|
||||
temp_slots[slot_count].start_hour, temp_slots[slot_count].start_minute,
|
||||
temp_slots[slot_count].end_hour, temp_slots[slot_count].end_minute,
|
||||
temp_slots[slot_count].enabled ? "ENABLED" : "DISABLED");
|
||||
|
||||
slot_count++;
|
||||
}
|
||||
|
||||
DEBUG_PRINT("[Attendance] Parsed %d time slots\r\n", slot_count);
|
||||
|
||||
// 应用解析结果
|
||||
if (slot_count > 0) {
|
||||
Attendance_UpdateTimeSlots(temp_slots, slot_count);
|
||||
return slot_count;
|
||||
}
|
||||
|
||||
DEBUG_ERROR("[Attendance] Failed to parse any time slots");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置当前时间（由外部定期调用更新）
|
||||
* @param hour 小时 (0-23)
|
||||
* @param minute 分钟 (0-59)
|
||||
*/
|
||||
void Attendance_SetCurrentTime(uint8_t hour, uint8_t minute)
|
||||
{
|
||||
current_hour = hour;
|
||||
current_minute = minute;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 获取当前所处的考勤时段
|
||||
* @retval 时段编号 (0-N)，如果不在任何时段内则返回 -1
|
||||
*/
|
||||
int8_t Attendance_GetCurrentTimeSlot(void)
|
||||
{
|
||||
for (uint8_t i = 0; i < time_slot_count; i++)
|
||||
{
|
||||
// 跳过禁用的时间段
|
||||
if (!time_slots[i].enabled) {
|
||||
continue;
|
||||
}
|
||||
|
||||
uint16_t current_minutes = current_hour * 60 + current_minute;
|
||||
uint16_t start_minutes = time_slots[i].start_hour * 60 + time_slots[i].start_minute;
|
||||
uint16_t end_minutes = time_slots[i].end_hour * 60 + time_slots[i].end_minute;
|
||||
|
||||
if (current_minutes >= start_minutes && current_minutes <= end_minutes)
|
||||
{
|
||||
return i; // 返回时段编号
|
||||
}
|
||||
}
|
||||
|
||||
return -1; // 不在任何考勤时段内
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 获取当前时段的开始和结束时间
|
||||
* @param start_time 输出：开始时间（格式"HH:MM"）
|
||||
* @param end_time 输出：结束时间（格式"HH:MM"）
|
||||
*/
|
||||
void Attendance_GetCurrentSlotTime(char* start_time, char* end_time)
|
||||
{
|
||||
int8_t current_slot = Attendance_GetCurrentTimeSlot();
|
||||
|
||||
if (current_slot >= 0 && current_slot < time_slot_count) {
|
||||
sprintf(start_time, "%02d:%02d",
|
||||
time_slots[current_slot].start_hour,
|
||||
time_slots[current_slot].start_minute);
|
||||
sprintf(end_time, "%02d:%02d",
|
||||
time_slots[current_slot].end_hour,
|
||||
time_slots[current_slot].end_minute);
|
||||
} else {
|
||||
// 不在任何时段，返回全天
|
||||
strcpy(start_time, "00:00");
|
||||
strcpy(end_time, "23:59");
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 检查学生是否在服务器端已签到（服务器端查重）
|
||||
* @param student_id 学生学号
|
||||
* @retval 1=服务器显示已签到（重复）, 0=未签到或查询失败
|
||||
*/
|
||||
uint8_t Attendance_IsDuplicateOnServer(const char* student_id)
|
||||
{
|
||||
char slot_start[8];
|
||||
char slot_end[8];
|
||||
|
||||
// 获取当前时段时间
|
||||
Attendance_GetCurrentSlotTime(slot_start, slot_end);
|
||||
|
||||
DEBUG_PRINT("[Attendance] Checking server for duplicate: %s (%s-%s)\r\n",
|
||||
student_id, slot_start, slot_end);
|
||||
|
||||
// 调用ESP8266查询服务器（这个过程可能耗时，蜂鸣器状态由调用者控制）
|
||||
return ESP8266_CheckDuplicate(student_id, slot_start, slot_end);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 检查是否在当前时段重复打卡（本地+服务器）
|
||||
* @param student_id 学生学号
|
||||
* @retval 1=重复, 0=不重复
|
||||
*/
|
||||
uint8_t Attendance_IsDuplicate(const char* student_id)
|
||||
{
|
||||
int8_t current_slot = Attendance_GetCurrentTimeSlot();
|
||||
|
||||
if (current_slot < 0) {
|
||||
return 0; // 不在考勤时段，不算重复
|
||||
}
|
||||
|
||||
// 遍历现有记录，检查是否在当前时段已打卡
|
||||
for (uint16_t i = 0; i < record_count; i++)
|
||||
{
|
||||
// 如果找到相同学号且在相同时段
|
||||
if (strcmp(attendance_records[i].student_id, student_id) == 0 &&
|
||||
attendance_records[i].time_slot == current_slot)
|
||||
{
|
||||
return 1; // 本时段已打卡，重复
|
||||
}
|
||||
}
|
||||
|
||||
return 0; // 不重复
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 处理人脸识别结果并记录考勤
|
||||
* @param result 人脸识别结果
|
||||
* @retval 考勤状态
|
||||
*/
|
||||
AttendanceStatus Attendance_ProcessFaceResult(FaceRecognitionResult* result)
|
||||
{
|
||||
// 1. 检查识别是否成功
|
||||
if (result->success == 0)
|
||||
{
|
||||
return ATTENDANCE_UNKNOWN;
|
||||
}
|
||||
|
||||
// 2. 检查置信度
|
||||
if (result->confidence < MIN_CONFIDENCE_THRESHOLD)
|
||||
{
|
||||
return ATTENDANCE_LOW_CONFIDENCE;
|
||||
}
|
||||
|
||||
// 3. 检查是否在考勤时段内
|
||||
int8_t current_slot = Attendance_GetCurrentTimeSlot();
|
||||
if (current_slot < 0)
|
||||
{
|
||||
DEBUG_PRINT("[Attendance] Not in time slot (Current: %02d:%02d)\r\n",
|
||||
current_hour, current_minute);
|
||||
return ATTENDANCE_OUT_OF_TIME;
|
||||
}
|
||||
|
||||
DEBUG_PRINT("[Attendance] Current slot: %s (%02d:%02d)\r\n",
|
||||
time_slots[current_slot].name, current_hour, current_minute);
|
||||
|
||||
// 4. 检查是否在当前时段重复打卡（本地记录检查）
|
||||
if (Attendance_IsDuplicate(result->student_id))
|
||||
{
|
||||
DEBUG_PRINT("[Attendance] Local duplicate in slot: %s\r\n", time_slots[current_slot].name);
|
||||
return ATTENDANCE_DUPLICATE;
|
||||
}
|
||||
|
||||
// 5. 检查缓存中是否已签到（从服务器下载的今日记录）
|
||||
if (Attendance_IsDuplicateInCache(result->student_id))
|
||||
{
|
||||
DEBUG_PRINT("[Attendance] Cache duplicate in slot: %s\r\n", time_slots[current_slot].name);
|
||||
return ATTENDANCE_DUPLICATE;
|
||||
}
|
||||
|
||||
// 6. 添加新记录
|
||||
if (record_count < MAX_ATTENDANCE_RECORDS)
|
||||
{
|
||||
// 复制学号和姓名
|
||||
strncpy(attendance_records[record_count].student_id, result->student_id, 19);
|
||||
attendance_records[record_count].student_id[19] = '\0';
|
||||
|
||||
strncpy(attendance_records[record_count].student_name, result->student_name, 31);
|
||||
attendance_records[record_count].student_name[31] = '\0';
|
||||
|
||||
// 记录置信度
|
||||
attendance_records[record_count].confidence = result->confidence;
|
||||
|
||||
// 记录时间戳和时段
|
||||
// 简化：使用系统运行时间戳（服务器会用接收时间替换）
|
||||
attendance_records[record_count].timestamp = Get_Time_ms() / 1000;
|
||||
attendance_records[record_count].time_slot = current_slot;
|
||||
|
||||
// 初始化同步状态
|
||||
attendance_records[record_count].sync_status = SYNC_PENDING;
|
||||
attendance_records[record_count].retry_count = 0;
|
||||
attendance_records[record_count].last_retry_time = 0;
|
||||
|
||||
record_count++;
|
||||
total_attendance_count++;
|
||||
|
||||
// 添加到缓存，防止重复签到
|
||||
Attendance_AddToCache(result->student_id);
|
||||
|
||||
DEBUG_PRINT("[Attendance] Success! Slot=%s, Total=%d, Status=PENDING\r\n",
|
||||
time_slots[current_slot].name, total_attendance_count);
|
||||
|
||||
return ATTENDANCE_SUCCESS;
|
||||
}
|
||||
else
|
||||
{
|
||||
// 记录已满，覆盖最早的记录
|
||||
memmove(&attendance_records[0], &attendance_records[1],
|
||||
sizeof(AttendanceRecord) * (MAX_ATTENDANCE_RECORDS - 1));
|
||||
record_count = MAX_ATTENDANCE_RECORDS - 1;
|
||||
|
||||
// 在最后位置添加新记录
|
||||
strncpy(attendance_records[record_count].student_id, result->student_id, 19);
|
||||
attendance_records[record_count].student_id[19] = '\0';
|
||||
strncpy(attendance_records[record_count].student_name, result->student_name, 31);
|
||||
attendance_records[record_count].student_name[31] = '\0';
|
||||
attendance_records[record_count].confidence = result->confidence;
|
||||
|
||||
// 简化：使用系统运行时间戳（服务器会用接收时间替换）
|
||||
attendance_records[record_count].timestamp = Get_Time_ms() / 1000;
|
||||
attendance_records[record_count].time_slot = current_slot;
|
||||
attendance_records[record_count].sync_status = SYNC_PENDING;
|
||||
attendance_records[record_count].retry_count = 0;
|
||||
attendance_records[record_count].last_retry_time = 0;
|
||||
|
||||
record_count++;
|
||||
total_attendance_count++;
|
||||
|
||||
return ATTENDANCE_SUCCESS;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 清空所有考勤记录
|
||||
*/
|
||||
void Attendance_ClearRecords(void)
|
||||
{
|
||||
record_count = 0;
|
||||
memset(attendance_records, 0, sizeof(attendance_records));
|
||||
// 注意：不清空 total_attendance_count，保留历史统计
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 获取累计考勤总数
|
||||
*/
|
||||
uint16_t Attendance_GetTotalCount(void)
|
||||
{
|
||||
return total_attendance_count;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 获取当前缓存中的记录数
|
||||
*/
|
||||
uint16_t Attendance_GetActiveCount(void)
|
||||
{
|
||||
return record_count;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 获取待同步记录的数量（PENDING或FAILED状态）
|
||||
* @retval 待同步记录数
|
||||
*/
|
||||
uint16_t Attendance_GetPendingCount(void)
|
||||
{
|
||||
uint16_t count = 0;
|
||||
for (uint16_t i = 0; i < record_count; i++)
|
||||
{
|
||||
if (attendance_records[i].sync_status == SYNC_PENDING ||
|
||||
attendance_records[i].sync_status == SYNC_FAILED)
|
||||
{
|
||||
count++;
|
||||
}
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 获取下一个待同步的记录（PENDING或FAILED状态）
|
||||
* @param index 输出参数，返回记录的索引
|
||||
* @retval 记录指针，如果没有待同步记录则返回NULL
|
||||
*/
|
||||
AttendanceRecord* Attendance_GetNextPendingRecord(uint16_t* index)
|
||||
{
|
||||
uint32_t current_time = Get_Time_ms();
|
||||
|
||||
// 优先处理PENDING状态的记录
|
||||
for (uint16_t i = 0; i < record_count; i++)
|
||||
{
|
||||
if (attendance_records[i].sync_status == SYNC_PENDING)
|
||||
{
|
||||
if (index != NULL)
|
||||
{
|
||||
*index = i;
|
||||
}
|
||||
return &attendance_records[i];
|
||||
}
|
||||
}
|
||||
|
||||
// 然后处理FAILED状态的记录（需要等待重试间隔）
|
||||
for (uint16_t i = 0; i < record_count; i++)
|
||||
{
|
||||
if (attendance_records[i].sync_status == SYNC_FAILED)
|
||||
{
|
||||
// 指数退避算法：重试间隔 = 2^retry_count * 1000ms (最大30秒)
|
||||
uint32_t retry_interval = (1 << attendance_records[i].retry_count) * 1000;
|
||||
if (retry_interval > 30000) retry_interval = 30000;
|
||||
|
||||
// 检查是否到达重试时间
|
||||
if (current_time - attendance_records[i].last_retry_time >= retry_interval)
|
||||
{
|
||||
if (index != NULL)
|
||||
{
|
||||
*index = i;
|
||||
}
|
||||
return &attendance_records[i];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return NULL; // 没有待同步记录
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 更新记录的同步状态
|
||||
* @param index 记录索引
|
||||
* @param status 新的同步状态
|
||||
*/
|
||||
void Attendance_MarkSyncStatus(uint16_t index, SyncStatus status)
|
||||
{
|
||||
if (index < record_count)
|
||||
{
|
||||
attendance_records[index].sync_status = status;
|
||||
|
||||
if (status == SYNC_FAILED || status == SYNC_SYNCING)
|
||||
{
|
||||
attendance_records[index].last_retry_time = Get_Time_ms();
|
||||
}
|
||||
|
||||
const char* status_str[] = {"PENDING", "SYNCING", "SYNCED", "FAILED"};
|
||||
DEBUG_PRINT("[Attendance] Record %d status: %s (ID=%s)\r\n",
|
||||
index, status_str[status], attendance_records[index].student_id);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 增加记录的重试计数
|
||||
* @param index 记录索引
|
||||
*/
|
||||
void Attendance_IncrementRetry(uint16_t index)
|
||||
{
|
||||
if (index < record_count)
|
||||
{
|
||||
attendance_records[index].retry_count++;
|
||||
DEBUG_PRINT("[Attendance] Record %d retry count: %d\r\n",
|
||||
index, attendance_records[index].retry_count);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 将所有FAILED记录重置为PENDING（用于网络恢复后）
|
||||
*/
|
||||
void Attendance_ResetFailedRecords(void)
|
||||
{
|
||||
uint16_t reset_count = 0;
|
||||
for (uint16_t i = 0; i < record_count; i++)
|
||||
{
|
||||
if (attendance_records[i].sync_status == SYNC_FAILED)
|
||||
{
|
||||
attendance_records[i].sync_status = SYNC_PENDING;
|
||||
attendance_records[i].retry_count = 0;
|
||||
reset_count++;
|
||||
}
|
||||
}
|
||||
|
||||
if (reset_count > 0)
|
||||
{
|
||||
DEBUG_PRINT("[Attendance] Reset %d failed records to pending\r\n", reset_count);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 按索引获取记录
|
||||
* @param index 记录索引
|
||||
* @retval 记录指针，如果索引无效则返回NULL
|
||||
*/
|
||||
AttendanceRecord* Attendance_GetRecordByIndex(uint16_t index)
|
||||
{
|
||||
if (index < record_count)
|
||||
{
|
||||
return &attendance_records[index];
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
@@ -0,0 +1,79 @@
|
||||
#ifndef __ATTENDANCE_H
|
||||
#define __ATTENDANCE_H
|
||||
|
||||
#include "stm32f10x.h"
|
||||
|
||||
// 同步状态枚举
|
||||
typedef enum {
|
||||
SYNC_PENDING = 0, // 待同步（新记录）
|
||||
SYNC_SYNCING, // 同步中
|
||||
SYNC_SYNCED, // 已同步成功
|
||||
SYNC_FAILED // 同步失败（等待重试）
|
||||
} SyncStatus;
|
||||
|
||||
// 考勤记录结构体
|
||||
typedef struct {
|
||||
char student_id[20]; // 学号
|
||||
char student_name[32]; // 学生姓名
|
||||
float confidence; // 识别置信度
|
||||
uint32_t timestamp; // 打卡时间戳（秒）
|
||||
uint8_t time_slot; // 打卡时段编号
|
||||
SyncStatus sync_status; // 同步状态
|
||||
uint8_t retry_count; // 重试次数
|
||||
uint32_t last_retry_time; // 上次重试时间（毫秒）
|
||||
} AttendanceRecord;
|
||||
|
||||
// 人脸识别结果结构体
|
||||
typedef struct {
|
||||
uint8_t success; // 识别是否成功 (1=成功, 0=失败)
|
||||
char student_id[20]; // 学号
|
||||
char student_name[32]; // 学生姓名
|
||||
float confidence; // 置信度 (0.0-1.0)
|
||||
} FaceRecognitionResult;
|
||||
|
||||
// 考勤状态
|
||||
typedef enum {
|
||||
ATTENDANCE_SUCCESS = 0, // 打卡成功
|
||||
ATTENDANCE_DUPLICATE, // 重复打卡（本时段已打卡）
|
||||
ATTENDANCE_UNKNOWN, // 未识别到人脸
|
||||
ATTENDANCE_LOW_CONFIDENCE, // 置信度过低
|
||||
ATTENDANCE_OUT_OF_TIME // 不在考勤时间段内
|
||||
} AttendanceStatus;
|
||||
|
||||
// 时间段定义结构体
|
||||
typedef struct {
|
||||
uint8_t enabled; // 是否启用该时间段（1=启用, 0=禁用）
|
||||
uint8_t start_hour; // 开始小时 (0-23)
|
||||
uint8_t start_minute; // 开始分钟 (0-59)
|
||||
uint8_t end_hour; // 结束小时 (0-23)
|
||||
uint8_t end_minute; // 结束分钟 (0-59)
|
||||
char name[20]; // 时段名称（如"上午签到"）
|
||||
} TimeSlot;
|
||||
|
||||
// 函数声明
|
||||
void Attendance_Init(void);
|
||||
void Attendance_SetCurrentTime(uint8_t hour, uint8_t minute); // 设置当前时间
|
||||
void Attendance_UpdateTimeSlots(TimeSlot* slots, uint8_t count); // 更新时间段配置（从服务器下载后调用）
|
||||
uint8_t Attendance_ParseTimeSlotsJSON(const char* json_str); // 从JSON字符串解析时间段配置
|
||||
AttendanceStatus Attendance_ProcessFaceResult(FaceRecognitionResult* result);
|
||||
uint8_t Attendance_IsDuplicate(const char* student_id);
|
||||
uint8_t Attendance_IsDuplicateOnServer(const char* student_id); // 服务器端查重
|
||||
void Attendance_GetCurrentSlotTime(char* start_time, char* end_time); // 获取当前时段时间
|
||||
uint8_t Attendance_LoadTodayRecordsFromServer(void); // 新增：从服务器加载今日签到记录
|
||||
uint8_t Attendance_IsDuplicateInCache(const char* student_id); // 新增：在本地缓存中查重
|
||||
void Attendance_AddToCache(const char* student_id); // 新增：添加学号到缓存
|
||||
void Attendance_ClearCache(void); // 新增：清空缓存
|
||||
void Attendance_ClearRecords(void);
|
||||
uint16_t Attendance_GetTotalCount(void); // 获取累计考勤总数
|
||||
uint16_t Attendance_GetActiveCount(void); // 获取当前缓存记录数
|
||||
int8_t Attendance_GetCurrentTimeSlot(void); // 获取当前时段编号（-1表示不在考勤时段）
|
||||
|
||||
// 数据同步相关函数
|
||||
uint16_t Attendance_GetPendingCount(void); // 获取待同步记录数量（PENDING状态）
|
||||
AttendanceRecord* Attendance_GetNextPendingRecord(uint16_t* index); // 获取下一个待同步记录
|
||||
void Attendance_MarkSyncStatus(uint16_t index, SyncStatus status); // 更新记录的同步状态
|
||||
void Attendance_IncrementRetry(uint16_t index); // 增加重试计数
|
||||
AttendanceRecord* Attendance_GetRecordByIndex(uint16_t index); // 按索引获取记录
|
||||
void Attendance_ResetFailedRecords(void); // 将所有FAILED记录重置为PENDING
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,29 @@
|
||||
#include "Buzzer_LED.h"
|
||||
|
||||
void Buzzer_LED_Init(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC, ENABLE);
|
||||
|
||||
// 释放PB4（默认是JTAG引脚），保留SWD调试
|
||||
GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE);
|
||||
|
||||
// 根据连接图.md: LED=PB4, 蜂鸣器=PB5
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
|
||||
// PC13板载状态指示LED
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
|
||||
// 初始状态：LED和蜂鸣器都关闭
|
||||
LED_SUCCESS_OFF();
|
||||
BUZZER_OFF();
|
||||
|
||||
// PC13状态LED：初始化时点亮（表示系统正在初始化）
|
||||
LED_STATUS_ON();
|
||||
}
|
||||
@@ -0,0 +1,19 @@
|
||||
#ifndef __BUZZER_LED_H
|
||||
#define __BUZZER_LED_H
|
||||
|
||||
#include "stm32f10x.h"
|
||||
|
||||
// 定义GPIO控制宏 (根据连接图.md修改)
|
||||
#define LED_SUCCESS_OFF() GPIO_ResetBits(GPIOB, GPIO_Pin_4) // PB4, 高电平点亮
|
||||
#define LED_SUCCESS_ON() GPIO_SetBits(GPIOB, GPIO_Pin_4)
|
||||
#define BUZZER_OFF() GPIO_SetBits(GPIOB, GPIO_Pin_5) // PB5, 低电平触发
|
||||
#define BUZZER_ON() GPIO_ResetBits(GPIOB, GPIO_Pin_5)
|
||||
|
||||
// PC13板载状态指示LED (低电平点亮)
|
||||
#define LED_STATUS_ON() GPIO_ResetBits(GPIOC, GPIO_Pin_13) // 初始化中：常亮
|
||||
#define LED_STATUS_OFF() GPIO_SetBits(GPIOC, GPIO_Pin_13) // 就绪后：熄灭
|
||||
|
||||
// 声明初始化函数
|
||||
void Buzzer_LED_Init(void);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,99 @@
|
||||
/*
|
||||
* 加密模块实现
|
||||
* 使用AES-128-CBC + Base64编码
|
||||
*/
|
||||
|
||||
#include "Crypto.h"
|
||||
#include "aes.h"
|
||||
#include "base64.h"
|
||||
#include <string.h>
|
||||
|
||||
// ⚠️ 重要：密钥和IV必须与服务器端完全一致！
|
||||
// AES-128密钥（16字节）
|
||||
static const uint8_t AES_KEY[16] = {
|
||||
0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6,
|
||||
0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c
|
||||
};
|
||||
|
||||
// 初始化向量（16字节）
|
||||
static const uint8_t AES_IV[16] = {
|
||||
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
|
||||
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f
|
||||
};
|
||||
|
||||
static struct AES_ctx aes_ctx;
|
||||
|
||||
void Crypto_Init(void)
|
||||
{
|
||||
// 初始化AES上下文（使用CBC模式）
|
||||
AES_init_ctx_iv(&aes_ctx, AES_KEY, AES_IV);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PKCS#7填充
|
||||
* 将数据填充到16字节的倍数
|
||||
*/
|
||||
static uint32_t pkcs7_pad(uint8_t* data, uint32_t data_len, uint32_t buffer_size)
|
||||
{
|
||||
// 计算需要填充的字节数
|
||||
uint32_t padding_len = 16 - (data_len % 16);
|
||||
|
||||
// 检查缓冲区是否足够
|
||||
if (data_len + padding_len > buffer_size) {
|
||||
return 0; // 缓冲区不足
|
||||
}
|
||||
|
||||
// 填充（PKCS#7标准）
|
||||
uint32_t i;
|
||||
for (i = 0; i < padding_len; i++) {
|
||||
data[data_len + i] = (uint8_t)padding_len;
|
||||
}
|
||||
|
||||
return data_len + padding_len;
|
||||
}
|
||||
|
||||
uint32_t Crypto_EncryptJSON(const char* json_data, char* encrypted_output)
|
||||
{
|
||||
uint32_t json_len = strlen(json_data);
|
||||
uint8_t buffer[512]; // 临时缓冲区
|
||||
|
||||
// 1. 复制JSON数据到缓冲区
|
||||
if (json_len > sizeof(buffer) - 16) {
|
||||
return 0; // 数据太长
|
||||
}
|
||||
memcpy(buffer, json_data, json_len);
|
||||
|
||||
// 2. PKCS#7填充到16字节的倍数
|
||||
uint32_t padded_len = pkcs7_pad(buffer, json_len, sizeof(buffer));
|
||||
if (padded_len == 0) {
|
||||
return 0; // 填充失败
|
||||
}
|
||||
|
||||
// 3. 手动实现标准CBC加密（绕过aes.c的bug）
|
||||
struct AES_ctx ctx;
|
||||
uint8_t iv[16];
|
||||
uint32_t i, j;
|
||||
|
||||
// 初始化密钥和IV
|
||||
AES_init_ctx(&ctx, AES_KEY);
|
||||
memcpy(iv, AES_IV, 16);
|
||||
|
||||
// CBC加密：每个块先XOR IV，再加密，然后用密文更新IV
|
||||
for (i = 0; i < padded_len; i += 16) {
|
||||
// XOR with IV
|
||||
for (j = 0; j < 16; j++) {
|
||||
buffer[i + j] ^= iv[j];
|
||||
}
|
||||
|
||||
// AES加密单个块
|
||||
AES_ECB_encrypt(&ctx, &buffer[i]);
|
||||
|
||||
// 更新IV为当前密文块
|
||||
memcpy(iv, &buffer[i], 16);
|
||||
}
|
||||
|
||||
// 4. Base64编码
|
||||
uint32_t encoded_len = base64_encode(buffer, padded_len, encrypted_output);
|
||||
|
||||
return encoded_len;
|
||||
}
|
||||
@@ -0,0 +1,30 @@
|
||||
#ifndef _CRYPTO_H_
|
||||
#define _CRYPTO_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
|
||||
/**
|
||||
* @brief 加密JSON数据
|
||||
* @param json_data 原始JSON字符串
|
||||
* @param encrypted_output 输出的加密Base64字符串（需要预分配足够空间）
|
||||
* @return 加密后的Base64字符串长度
|
||||
*
|
||||
* 注意：encrypted_output缓冲区至少需要 (strlen(json_data) / 16 + 1) * 16 * 4/3 + 10 字节
|
||||
*/
|
||||
uint32_t Crypto_EncryptJSON(const char* json_data, char* encrypted_output);
|
||||
|
||||
/**
|
||||
* @brief 获取加密后数据的最大长度
|
||||
* @param json_length JSON字符串长度
|
||||
* @return 加密后的最大长度
|
||||
*/
|
||||
#define CRYPTO_MAX_ENCRYPTED_SIZE(json_len) (((json_len) / 16 + 1) * 16 * 4 / 3 + 10)
|
||||
|
||||
/**
|
||||
* @brief 初始化加密模块
|
||||
* 设置密钥和IV（初始化向量）
|
||||
*/
|
||||
void Crypto_Init(void);
|
||||
|
||||
#endif // _CRYPTO_H_
|
||||
@@ -0,0 +1,246 @@
|
||||
#include "DS1302.h"
|
||||
#include "Delay.h"
|
||||
|
||||
// 根据连接图.md: DS1302引脚配置
|
||||
// CLK: PA4, DAT: PA5, RST: PA6
|
||||
|
||||
#define DS1302_SCLK_PIN GPIO_Pin_4 // CLK
|
||||
#define DS1302_IO_PIN GPIO_Pin_5 // DAT (双向)
|
||||
#define DS1302_CE_PIN GPIO_Pin_6 // RST/CE
|
||||
#define DS1302_GPIO GPIOA
|
||||
|
||||
// GPIO控制宏
|
||||
#define SCLK_H GPIO_SetBits(DS1302_GPIO, DS1302_SCLK_PIN)
|
||||
#define SCLK_L GPIO_ResetBits(DS1302_GPIO, DS1302_SCLK_PIN)
|
||||
#define DATA_H GPIO_SetBits(DS1302_GPIO, DS1302_IO_PIN)
|
||||
#define DATA_L GPIO_ResetBits(DS1302_GPIO, DS1302_IO_PIN)
|
||||
#define CE_H GPIO_SetBits(DS1302_GPIO, DS1302_CE_PIN)
|
||||
#define CE_L GPIO_ResetBits(DS1302_GPIO, DS1302_CE_PIN)
|
||||
#define DATA_READ GPIO_ReadInputDataBit(DS1302_GPIO, DS1302_IO_PIN)
|
||||
|
||||
// DS1302寄存器地址（写地址）
|
||||
#define DS1302_SECOND 0x80
|
||||
#define DS1302_MINUTE 0x82
|
||||
#define DS1302_HOUR 0x84
|
||||
#define DS1302_DATE 0x86
|
||||
#define DS1302_MONTH 0x88
|
||||
#define DS1302_DAY 0x8A
|
||||
#define DS1302_YEAR 0x8C
|
||||
#define DS1302_WP 0x8E
|
||||
|
||||
// BCD码转换
|
||||
#define BCD_TO_DEC(bcd) (((bcd) >> 4) * 10 + ((bcd) & 0x0F))
|
||||
#define DEC_TO_BCD(dec) ((((dec) / 10) << 4) | ((dec) % 10))
|
||||
|
||||
// 微秒延时
|
||||
static void delay_us(uint32_t us)
|
||||
{
|
||||
volatile uint32_t i;
|
||||
while (us--) {
|
||||
for (i = 0; i < 12; i++); // 72MHz下约1us
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 配置IO口为输出
|
||||
*/
|
||||
static void DS1302_DATAOUT_init(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
GPIO_InitStructure.GPIO_Pin = DS1302_IO_PIN;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(DS1302_GPIO, &GPIO_InitStructure);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 配置IO口为输入
|
||||
*/
|
||||
static void DS1302_DATAINPUT_init(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
GPIO_InitStructure.GPIO_Pin = DS1302_IO_PIN;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||
GPIO_Init(DS1302_GPIO, &GPIO_InitStructure);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DS1302初始化
|
||||
*/
|
||||
void DS1302_Init(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
|
||||
// 使能GPIOA时钟
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
|
||||
|
||||
// 配置SCLK和CE为推挽输出
|
||||
GPIO_InitStructure.GPIO_Pin = DS1302_SCLK_PIN | DS1302_CE_PIN;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(DS1302_GPIO, &GPIO_InitStructure);
|
||||
|
||||
// 配置IO为输出（初始状态）
|
||||
DS1302_DATAOUT_init();
|
||||
|
||||
// 初始化引脚状态
|
||||
SCLK_L;
|
||||
CE_L;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 向DS1302发送一字节数据（根据demo代码）
|
||||
* @param data 要发送的数据
|
||||
*/
|
||||
static void DS1302_write_onebyte(uint8_t data)
|
||||
{
|
||||
uint8_t count = 0;
|
||||
|
||||
DS1302_DATAOUT_init(); // 配置为输出
|
||||
SCLK_L;
|
||||
|
||||
for (count = 0; count < 8; count++)
|
||||
{
|
||||
SCLK_L;
|
||||
|
||||
// 先准备好数据再发送
|
||||
if (data & 0x01)
|
||||
DATA_H;
|
||||
else
|
||||
DATA_L;
|
||||
|
||||
SCLK_H; // 拉高时钟线，发送数据
|
||||
data >>= 1;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 向指定寄存器地址发送数据（根据demo代码）
|
||||
* @param address 寄存器地址
|
||||
* @param data 数据
|
||||
*/
|
||||
void DS1302_WriteByte(uint8_t address, uint8_t data)
|
||||
{
|
||||
CE_L;
|
||||
SCLK_L;
|
||||
delay_us(1);
|
||||
|
||||
CE_H;
|
||||
delay_us(2);
|
||||
|
||||
DS1302_write_onebyte(address);
|
||||
DS1302_write_onebyte(data);
|
||||
|
||||
CE_L;
|
||||
SCLK_L;
|
||||
delay_us(2);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 从指定地址读取一字节数据（根据demo代码）
|
||||
* @param address 寄存器地址
|
||||
* @retval 读取到的数据
|
||||
*/
|
||||
uint8_t DS1302_ReadByte(uint8_t address)
|
||||
{
|
||||
uint8_t count = 0;
|
||||
uint8_t return_data = 0x00;
|
||||
|
||||
CE_L;
|
||||
SCLK_L;
|
||||
delay_us(3);
|
||||
|
||||
CE_H;
|
||||
delay_us(3);
|
||||
|
||||
DS1302_write_onebyte(address);
|
||||
|
||||
DS1302_DATAINPUT_init(); // 配置I/O口为输入
|
||||
delay_us(2);
|
||||
|
||||
for (count = 0; count < 8; count++)
|
||||
{
|
||||
delay_us(2); // 使电平持续一段时间
|
||||
return_data >>= 1;
|
||||
|
||||
SCLK_H;
|
||||
delay_us(4); // 使高电平持续一段时间
|
||||
|
||||
SCLK_L;
|
||||
delay_us(14); // ⭐ 关键延时：延时14us后再去读取电压，更加准确
|
||||
|
||||
if (DATA_READ)
|
||||
return_data = return_data | 0x80;
|
||||
}
|
||||
|
||||
delay_us(2);
|
||||
CE_L;
|
||||
DATA_L;
|
||||
|
||||
return return_data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置DS1302时间
|
||||
* @param time 时间结构体指针
|
||||
*/
|
||||
void DS1302_SetTime(DS1302_Time* time)
|
||||
{
|
||||
// 关闭写保护
|
||||
DS1302_WriteByte(DS1302_WP, 0x00);
|
||||
|
||||
// 写入时间数据（BCD码格式）
|
||||
DS1302_WriteByte(DS1302_SECOND, DEC_TO_BCD(time->second));
|
||||
DS1302_WriteByte(DS1302_MINUTE, DEC_TO_BCD(time->minute));
|
||||
DS1302_WriteByte(DS1302_HOUR, DEC_TO_BCD(time->hour));
|
||||
DS1302_WriteByte(DS1302_DATE, DEC_TO_BCD(time->day));
|
||||
DS1302_WriteByte(DS1302_MONTH, DEC_TO_BCD(time->month));
|
||||
DS1302_WriteByte(DS1302_DAY, DEC_TO_BCD(time->week));
|
||||
DS1302_WriteByte(DS1302_YEAR, DEC_TO_BCD(time->year % 100));
|
||||
|
||||
// 开启写保护
|
||||
DS1302_WriteByte(DS1302_WP, 0x80);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 读取DS1302时间
|
||||
* @param time 时间结构体指针
|
||||
*/
|
||||
void DS1302_GetTime(DS1302_Time* time)
|
||||
{
|
||||
uint8_t read_time[7];
|
||||
uint8_t hour_reg;
|
||||
|
||||
// 读取时间数据（BCD码）
|
||||
read_time[0] = DS1302_ReadByte(0x81); // 读秒
|
||||
read_time[1] = DS1302_ReadByte(0x83); // 读分
|
||||
read_time[2] = DS1302_ReadByte(0x85); // 读时
|
||||
read_time[3] = DS1302_ReadByte(0x87); // 读日
|
||||
read_time[4] = DS1302_ReadByte(0x89); // 读月
|
||||
read_time[5] = DS1302_ReadByte(0x8B); // 读星期
|
||||
read_time[6] = DS1302_ReadByte(0x8D); // 读年
|
||||
|
||||
// BCD码转换为10进制（先屏蔽控制位，再转换）
|
||||
time->second = BCD_TO_DEC(read_time[0] & 0x7F); // bit7=CH
|
||||
time->minute = BCD_TO_DEC(read_time[1] & 0x7F);
|
||||
|
||||
hour_reg = read_time[2];
|
||||
if (hour_reg & 0x80) {
|
||||
// 12小时制：bit5=PM, bit4~0=小时(1~12)
|
||||
uint8_t hour12 = BCD_TO_DEC(hour_reg & 0x1F);
|
||||
uint8_t is_pm = (hour_reg & 0x20) ? 1 : 0;
|
||||
if (hour12 == 12) {
|
||||
time->hour = is_pm ? 12 : 0;
|
||||
} else {
|
||||
time->hour = is_pm ? (hour12 + 12) : hour12;
|
||||
}
|
||||
} else {
|
||||
// 24小时制：bit5~0=小时(0~23)
|
||||
time->hour = BCD_TO_DEC(hour_reg & 0x3F);
|
||||
}
|
||||
|
||||
time->day = BCD_TO_DEC(read_time[3] & 0x3F);
|
||||
time->month = BCD_TO_DEC(read_time[4] & 0x1F);
|
||||
time->week = read_time[5] & 0x07;
|
||||
time->year = BCD_TO_DEC(read_time[6]) + 2000;
|
||||
}
|
||||
@@ -0,0 +1,24 @@
|
||||
#ifndef __DS1302_H
|
||||
#define __DS1302_H
|
||||
|
||||
#include "stm32f10x.h"
|
||||
|
||||
// DS1302时间结构体
|
||||
typedef struct {
|
||||
uint16_t year; // 年份 (2000-2099)
|
||||
uint8_t month; // 月份 (1-12)
|
||||
uint8_t day; // 日期 (1-31)
|
||||
uint8_t hour; // 小时 (0-23)
|
||||
uint8_t minute; // 分钟 (0-59)
|
||||
uint8_t second; // 秒钟 (0-59)
|
||||
uint8_t week; // 星期 (1-7, 1=周一)
|
||||
} DS1302_Time;
|
||||
|
||||
// 函数声明
|
||||
void DS1302_Init(void);
|
||||
void DS1302_SetTime(DS1302_Time* time);
|
||||
void DS1302_GetTime(DS1302_Time* time);
|
||||
uint8_t DS1302_ReadByte(uint8_t addr);
|
||||
void DS1302_WriteByte(uint8_t addr, uint8_t dat);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,136 @@
|
||||
#include "K210_USART.h"
|
||||
#include "Debug.h" // 添加调试支持
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
// 引用来自 main.c 的全局变量
|
||||
extern volatile char g_k210_rx_buffer[];
|
||||
extern volatile uint16_t g_k210_rx_counter;
|
||||
extern volatile uint8_t g_k210_rx_flag;
|
||||
|
||||
// 全局变量：存储解析后的人脸识别结果
|
||||
FaceRecognitionResult K210_FaceResult;
|
||||
|
||||
void K210_USART_Init(void)
|
||||
{
|
||||
// 根据连接图.md: K210使用USART3 (PB10/PB11)
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
USART_InitTypeDef USART_InitStructure;
|
||||
NVIC_InitTypeDef NVIC_InitStructure;
|
||||
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
|
||||
|
||||
// PB10: USART3_TX
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
|
||||
// PB11: USART3_RX
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
|
||||
USART_InitStructure.USART_BaudRate = 115200;
|
||||
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
|
||||
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
||||
USART_InitStructure.USART_Parity = USART_Parity_No;
|
||||
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||
USART_Init(USART3, &USART_InitStructure);
|
||||
|
||||
USART_ITConfig(USART3, USART_IT_RXNE, ENABLE);
|
||||
|
||||
NVIC_InitStructure.NVIC_IRQChannel = USART3_IRQn;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
|
||||
USART_Cmd(USART3, ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 解析K210发送的人脸识别数据
|
||||
* @param buffer 接收到的数据缓冲区
|
||||
* @param result 解析结果存储结构体
|
||||
* @retval 1=解析成功, 0=解析失败
|
||||
*
|
||||
* K210数据格式示例: "ID:2021001,NAME:Zhang_San,CONF:0.95"
|
||||
* 或者: "UNKNOWN" (未识别到人脸)
|
||||
*/
|
||||
uint8_t K210_ParseFaceData(const char* buffer, FaceRecognitionResult* result)
|
||||
{
|
||||
DEBUG_PRINT("[K210] Raw data: %s\r\n", buffer);
|
||||
|
||||
// 清空结果结构体
|
||||
memset(result, 0, sizeof(FaceRecognitionResult));
|
||||
|
||||
// 检查是否为未识别
|
||||
if (strstr(buffer, "UNKNOWN") != NULL)
|
||||
{
|
||||
DEBUG_INFO("[K210] Unknown face detected");
|
||||
result->success = 0;
|
||||
strcpy(result->student_name, "Unknown");
|
||||
return 1;
|
||||
}
|
||||
|
||||
// 尝试解析完整数据
|
||||
char id[20] = {0};
|
||||
char name[32] = {0};
|
||||
float conf = 0.0f;
|
||||
|
||||
// 解析格式: ID:2021001,NAME:Zhang_San,CONF:0.95
|
||||
int parsed = sscanf(buffer, "ID:%19[^,],NAME:%31[^,],CONF:%f", id, name, &conf);
|
||||
|
||||
if (parsed == 3)
|
||||
{
|
||||
DEBUG_PRINT("[K210] Parsed: ID=%s, Name=%s, Conf=%.2f\r\n", id, name, conf);
|
||||
|
||||
result->success = 1;
|
||||
strncpy(result->student_id, id, 19);
|
||||
result->student_id[19] = '\0';
|
||||
|
||||
// 将下划线替换为空格（方便显示）
|
||||
strncpy(result->student_name, name, 31);
|
||||
result->student_name[31] = '\0';
|
||||
for (int i = 0; result->student_name[i] != '\0'; i++)
|
||||
{
|
||||
if (result->student_name[i] == '_')
|
||||
result->student_name[i] = ' ';
|
||||
}
|
||||
|
||||
result->confidence = conf;
|
||||
return 1;
|
||||
}
|
||||
|
||||
DEBUG_ERROR("[K210] Parse failed!");
|
||||
return 0; // 解析失败
|
||||
}
|
||||
|
||||
uint8_t K210_GetRxFlag(void)
|
||||
{
|
||||
if (g_k210_rx_flag)
|
||||
{
|
||||
DEBUG_INFO("[K210] Data received, parsing...");
|
||||
|
||||
// 解析K210发送的人脸识别数据
|
||||
K210_ParseFaceData((const char*)g_k210_rx_buffer, &K210_FaceResult);
|
||||
|
||||
g_k210_rx_flag = 0; // 清除标志位
|
||||
g_k210_rx_counter = 0; // 重置计数器
|
||||
|
||||
// 清空缓冲区，防止数据粘连
|
||||
memset((void*)g_k210_rx_buffer, 0, K210_RX_BUFFER_SIZE);
|
||||
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void K210_ClearRxFlag(void)
|
||||
{
|
||||
g_k210_rx_flag = 0;
|
||||
g_k210_rx_counter = 0;
|
||||
}
|
||||
@@ -0,0 +1,18 @@
|
||||
#ifndef __K210_USART_H
|
||||
#define __K210_USART_H
|
||||
|
||||
#include "stm32f10x.h"
|
||||
#include "Attendance.h"
|
||||
|
||||
#define K210_RX_BUFFER_SIZE 128
|
||||
|
||||
// 声明外部变量
|
||||
extern FaceRecognitionResult K210_FaceResult;
|
||||
|
||||
// 声明公共函数
|
||||
void K210_USART_Init(void);
|
||||
uint8_t K210_GetRxFlag(void);
|
||||
void K210_ClearRxFlag(void);
|
||||
uint8_t K210_ParseFaceData(const char* buffer, FaceRecognitionResult* result);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,106 @@
|
||||
#include "LightSensor.h"
|
||||
|
||||
// 补光灯当前状态
|
||||
static uint8_t g_fill_light_on = 0;
|
||||
|
||||
/**
|
||||
* @brief 初始化光敏电阻ADC和补光灯GPIO
|
||||
*/
|
||||
void LightSensor_Init(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
ADC_InitTypeDef ADC_InitStructure;
|
||||
|
||||
// 1. 使能时钟
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB | RCC_APB2Periph_ADC1, ENABLE);
|
||||
|
||||
// 配置ADC时钟分频（ADC时钟不能超过14MHz）
|
||||
RCC_ADCCLKConfig(RCC_PCLK2_Div6); // 72MHz / 6 = 12MHz
|
||||
|
||||
// 2. 配置PB0为模拟输入（光敏电阻）
|
||||
GPIO_InitStructure.GPIO_Pin = LIGHT_SENSOR_PIN;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN; // 模拟输入
|
||||
GPIO_Init(LIGHT_SENSOR_PORT, &GPIO_InitStructure);
|
||||
|
||||
// 3. 配置PB1为推挽输出（补光灯）
|
||||
GPIO_InitStructure.GPIO_Pin = FILL_LIGHT_PIN;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(FILL_LIGHT_PORT, &GPIO_InitStructure);
|
||||
|
||||
// 4. 初始化ADC1
|
||||
ADC_DeInit(ADC1);
|
||||
|
||||
ADC_InitStructure.ADC_Mode = ADC_Mode_Independent; // 独立模式
|
||||
ADC_InitStructure.ADC_ScanConvMode = DISABLE; // 单通道模式
|
||||
ADC_InitStructure.ADC_ContinuousConvMode = DISABLE; // 单次转换
|
||||
ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None; // 软件触发
|
||||
ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; // 右对齐
|
||||
ADC_InitStructure.ADC_NbrOfChannel = 1; // 1个通道
|
||||
ADC_Init(ADC1, &ADC_InitStructure);
|
||||
|
||||
// 5. 配置ADC通道1，采样时间239.5周期（更稳定）
|
||||
ADC_RegularChannelConfig(ADC1, LIGHT_SENSOR_ADC_CH, 1, ADC_SampleTime_239Cycles5);
|
||||
|
||||
// 6. 使能ADC1
|
||||
ADC_Cmd(ADC1, ENABLE);
|
||||
|
||||
// 7. ADC校准
|
||||
ADC_ResetCalibration(ADC1);
|
||||
while (ADC_GetResetCalibrationStatus(ADC1));
|
||||
ADC_StartCalibration(ADC1);
|
||||
while (ADC_GetCalibrationStatus(ADC1));
|
||||
|
||||
// 8. 初始状态：补光灯关闭
|
||||
FILL_LIGHT_OFF();
|
||||
g_fill_light_on = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 获取光敏电阻ADC值
|
||||
* @return ADC值 (0-4095)，值越大表示光线越暗（电阻越大）
|
||||
*/
|
||||
uint16_t LightSensor_GetValue(void)
|
||||
{
|
||||
// 启动ADC转换
|
||||
ADC_SoftwareStartConvCmd(ADC1, ENABLE);
|
||||
|
||||
// 等待转换完成
|
||||
while (!ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC));
|
||||
|
||||
// 返回转换结果
|
||||
return ADC_GetConversionValue(ADC1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 更新补光灯状态（在主循环中定期调用）
|
||||
* 使用迟滞控制避免灯光频繁开关
|
||||
*/
|
||||
void LightSensor_Update(void)
|
||||
{
|
||||
uint16_t light_value = LightSensor_GetValue();
|
||||
|
||||
// 迟滞控制逻辑
|
||||
if (g_fill_light_on) {
|
||||
// 当前灯是亮的，只有光线足够亮时才关灯
|
||||
if (light_value < LIGHT_THRESHOLD_HIGH) {
|
||||
FILL_LIGHT_OFF();
|
||||
g_fill_light_on = 0;
|
||||
}
|
||||
} else {
|
||||
// 当前灯是灭的，只有光线足够暗时才开灯
|
||||
if (light_value > LIGHT_THRESHOLD_LOW) {
|
||||
FILL_LIGHT_ON();
|
||||
g_fill_light_on = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 获取补光灯当前状态
|
||||
* @return 1=亮，0=灭
|
||||
*/
|
||||
uint8_t LightSensor_IsLightOn(void)
|
||||
{
|
||||
return g_fill_light_on;
|
||||
}
|
||||
@@ -0,0 +1,30 @@
|
||||
#ifndef __LIGHTSENSOR_H
|
||||
#define __LIGHTSENSOR_H
|
||||
|
||||
#include "stm32f10x.h"
|
||||
|
||||
// 光敏电阻引脚定义
|
||||
#define LIGHT_SENSOR_PIN GPIO_Pin_0
|
||||
#define LIGHT_SENSOR_PORT GPIOB
|
||||
#define LIGHT_SENSOR_ADC_CH ADC_Channel_8 // PB0 对应 ADC1 通道8
|
||||
|
||||
// 补光灯引脚定义
|
||||
#define FILL_LIGHT_PIN GPIO_Pin_1
|
||||
#define FILL_LIGHT_PORT GPIOB
|
||||
|
||||
// 补光灯控制宏（根据实际电路调整，假设高电平点亮）
|
||||
#define FILL_LIGHT_ON() GPIO_SetBits(FILL_LIGHT_PORT, FILL_LIGHT_PIN)
|
||||
#define FILL_LIGHT_OFF() GPIO_ResetBits(FILL_LIGHT_PORT, FILL_LIGHT_PIN)
|
||||
|
||||
// 光线阈值配置（可根据实际环境调整）
|
||||
#define LIGHT_THRESHOLD_LOW 1500 // 低于此值开灯（光线暗）
|
||||
#define LIGHT_THRESHOLD_HIGH 2000 // 高于此值关灯（光线亮）
|
||||
// 使用迟滞区间避免频繁开关
|
||||
|
||||
// 函数声明
|
||||
void LightSensor_Init(void); // 初始化光敏电阻ADC和补光灯GPIO
|
||||
uint16_t LightSensor_GetValue(void); // 获取光敏电阻ADC值
|
||||
void LightSensor_Update(void); // 更新补光灯状态（主循环中调用）
|
||||
uint8_t LightSensor_IsLightOn(void); // 获取补光灯当前状态
|
||||
|
||||
#endif
|
||||
+258
@@ -0,0 +1,258 @@
|
||||
// ======================================================
|
||||
// OLED.c (最终修正版, 支持中文)
|
||||
// ======================================================
|
||||
#include "stm32f10x.h"
|
||||
#include "OLED_Font.h" // 包含ASCII和中文的字模
|
||||
|
||||
/*引脚配置*/
|
||||
#define OLED_W_SCL(x) GPIO_WriteBit(GPIOB, GPIO_Pin_8, (BitAction)(x))
|
||||
#define OLED_W_SDA(x) GPIO_WriteBit(GPIOB, GPIO_Pin_9, (BitAction)(x))
|
||||
|
||||
/* ... 从 OLED_I2C_Init() 到 OLED_ShowBinNum() 的所有函数保持不变 ... */
|
||||
/* ... 请确保您文件里这部分内容是完整的 ... */
|
||||
|
||||
/*引脚初始化*/
|
||||
void OLED_I2C_Init(void)
|
||||
{
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
|
||||
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
|
||||
OLED_W_SCL(1);
|
||||
OLED_W_SDA(1);
|
||||
}
|
||||
|
||||
void OLED_I2C_Start(void)
|
||||
{
|
||||
OLED_W_SDA(1);
|
||||
OLED_W_SCL(1);
|
||||
OLED_W_SDA(0);
|
||||
OLED_W_SCL(0);
|
||||
}
|
||||
|
||||
void OLED_I2C_Stop(void)
|
||||
{
|
||||
OLED_W_SDA(0);
|
||||
OLED_W_SCL(1);
|
||||
OLED_W_SDA(1);
|
||||
}
|
||||
|
||||
void OLED_I2C_SendByte(uint8_t Byte)
|
||||
{
|
||||
uint8_t i;
|
||||
for (i = 0; i < 8; i++)
|
||||
{
|
||||
OLED_W_SDA(Byte & (0x80 >> i));
|
||||
OLED_W_SCL(1);
|
||||
OLED_W_SCL(0);
|
||||
}
|
||||
OLED_W_SCL(1);
|
||||
OLED_W_SCL(0);
|
||||
}
|
||||
|
||||
void OLED_WriteCommand(uint8_t Command)
|
||||
{
|
||||
OLED_I2C_Start();
|
||||
OLED_I2C_SendByte(0x78);
|
||||
OLED_I2C_SendByte(0x00);
|
||||
OLED_I2C_SendByte(Command);
|
||||
OLED_I2C_Stop();
|
||||
}
|
||||
|
||||
void OLED_WriteData(uint8_t Data)
|
||||
{
|
||||
OLED_I2C_Start();
|
||||
OLED_I2C_SendByte(0x78);
|
||||
OLED_I2C_SendByte(0x40);
|
||||
OLED_I2C_SendByte(Data);
|
||||
OLED_I2C_Stop();
|
||||
}
|
||||
|
||||
void OLED_SetCursor(uint8_t Y, uint8_t X)
|
||||
{
|
||||
OLED_WriteCommand(0xB0 | Y);
|
||||
OLED_WriteCommand(0x10 | ((X & 0xF0) >> 4));
|
||||
OLED_WriteCommand(0x00 | (X & 0x0F));
|
||||
}
|
||||
|
||||
void OLED_Clear(void)
|
||||
{
|
||||
uint8_t i, j;
|
||||
for (j = 0; j < 8; j++)
|
||||
{
|
||||
OLED_SetCursor(j, 0);
|
||||
for(i = 0; i < 128; i++)
|
||||
{
|
||||
OLED_WriteData(0x00);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void OLED_ShowChar(uint8_t Line, uint8_t Column, char Char)
|
||||
{
|
||||
uint8_t i;
|
||||
OLED_SetCursor((Line - 1) * 2, (Column - 1) * 8);
|
||||
for (i = 0; i < 8; i++)
|
||||
{
|
||||
OLED_WriteData(OLED_F8x16[Char - ' '][i]);
|
||||
}
|
||||
OLED_SetCursor((Line - 1) * 2 + 1, (Column - 1) * 8);
|
||||
for (i = 0; i < 8; i++)
|
||||
{
|
||||
OLED_WriteData(OLED_F8x16[Char - ' '][i + 8]);
|
||||
}
|
||||
}
|
||||
|
||||
void OLED_ShowString(uint8_t Line, uint8_t Column, char *String)
|
||||
{
|
||||
uint8_t i;
|
||||
for (i = 0; String[i] != '\0'; i++)
|
||||
{
|
||||
OLED_ShowChar(Line, Column + i, String[i]);
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t OLED_Pow(uint32_t X, uint32_t Y)
|
||||
{
|
||||
uint32_t Result = 1;
|
||||
while (Y--)
|
||||
{
|
||||
Result *= X;
|
||||
}
|
||||
return Result;
|
||||
}
|
||||
|
||||
void OLED_ShowNum(uint8_t Line, uint8_t Column, uint32_t Number, uint8_t Length)
|
||||
{
|
||||
uint8_t i;
|
||||
for (i = 0; i < Length; i++)
|
||||
{
|
||||
OLED_ShowChar(Line, Column + i, Number / OLED_Pow(10, Length - i - 1) % 10 + '0');
|
||||
}
|
||||
}
|
||||
|
||||
void OLED_ShowSignedNum(uint8_t Line, uint8_t Column, int32_t Number, uint8_t Length)
|
||||
{
|
||||
uint8_t i;
|
||||
uint32_t Number1;
|
||||
if (Number >= 0)
|
||||
{
|
||||
OLED_ShowChar(Line, Column, '+');
|
||||
Number1 = Number;
|
||||
}
|
||||
else
|
||||
{
|
||||
OLED_ShowChar(Line, Column, '-');
|
||||
Number1 = -Number;
|
||||
}
|
||||
for (i = 0; i < Length; i++)
|
||||
{
|
||||
OLED_ShowChar(Line, Column + i + 1, Number1 / OLED_Pow(10, Length - i - 1) % 10 + '0');
|
||||
}
|
||||
}
|
||||
|
||||
void OLED_ShowHexNum(uint8_t Line, uint8_t Column, uint32_t Number, uint8_t Length)
|
||||
{
|
||||
uint8_t i, SingleNumber;
|
||||
for (i = 0; i < Length; i++)
|
||||
{
|
||||
SingleNumber = Number / OLED_Pow(16, Length - i - 1) % 16;
|
||||
if (SingleNumber < 10)
|
||||
{
|
||||
OLED_ShowChar(Line, Column + i, SingleNumber + '0');
|
||||
}
|
||||
else
|
||||
{
|
||||
OLED_ShowChar(Line, Column + i, SingleNumber - 10 + 'A');
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void OLED_ShowBinNum(uint8_t Line, uint8_t Column, uint32_t Number, uint8_t Length)
|
||||
{
|
||||
uint8_t i;
|
||||
for (i = 0; i < Length; i++)
|
||||
{
|
||||
OLED_ShowChar(Line, Column + i, Number / OLED_Pow(2, Length - i - 1) % 2 + '0');
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief OLED显示一个16*16的汉字
|
||||
* @param Line 行位置，范围：1~4 (一个汉字占用2行高度)
|
||||
* @param Column 列位置，范围：1~8 (一个汉字占用2个字符宽度)
|
||||
* @param num 要显示的汉字在OLED_F16x16_CN字模数组中的索引
|
||||
* @retval 无
|
||||
*/
|
||||
void OLED_ShowChinese(uint8_t Line, uint8_t Column, uint8_t num)
|
||||
{
|
||||
uint8_t i;
|
||||
// 计算X坐标：一个汉字宽度为16像素，等于2个8像素的字符宽度
|
||||
uint8_t x = (Column - 1) * 16;
|
||||
// 计算Y坐标：一个汉字高度为16像素，等于2个8像素的行（页）高度
|
||||
uint8_t y = (Line - 1) * 2;
|
||||
|
||||
// 检查坐标是否越界
|
||||
if (x > 127 || y > 7) return;
|
||||
|
||||
// 显示上半部分 (16*8)
|
||||
OLED_SetCursor(y, x);
|
||||
for (i = 0; i < 16; i++)
|
||||
{
|
||||
OLED_WriteData(OLED_F16x16_CN[num][i]);
|
||||
}
|
||||
|
||||
// 显示下半部分 (16*8)
|
||||
OLED_SetCursor(y + 1, x);
|
||||
for (i = 0; i < 16; i++)
|
||||
{
|
||||
OLED_WriteData(OLED_F16x16_CN[num][i + 16]);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* ... OLED_Init() 函数保持不变 ... */
|
||||
void OLED_Init(void)
|
||||
{
|
||||
uint32_t i, j;
|
||||
|
||||
for (i = 0; i < 1000; i++)
|
||||
{
|
||||
for (j = 0; j < 1000; j++);
|
||||
}
|
||||
|
||||
OLED_I2C_Init();
|
||||
|
||||
OLED_WriteCommand(0xAE); //关闭显示
|
||||
OLED_WriteCommand(0xD5); //设置显示时钟分频比/振荡器频率
|
||||
OLED_WriteCommand(0x80);
|
||||
OLED_WriteCommand(0xA8); //设置多路复用率
|
||||
OLED_WriteCommand(0x3F);
|
||||
OLED_WriteCommand(0xD3); //设置显示偏移
|
||||
OLED_WriteCommand(0x00);
|
||||
OLED_WriteCommand(0x40); //设置显示开始行
|
||||
OLED_WriteCommand(0xA1); //设置左右方向，0xA1正常 0xA0左右反置
|
||||
OLED_WriteCommand(0xC8); //设置上下方向，0xC8正常 0xC0上下反置
|
||||
OLED_WriteCommand(0xDA); //设置COM引脚硬件配置
|
||||
OLED_WriteCommand(0x12);
|
||||
OLED_WriteCommand(0x81); //设置对比度控制
|
||||
OLED_WriteCommand(0xCF);
|
||||
OLED_WriteCommand(0xD9); //设置预充电周期
|
||||
OLED_WriteCommand(0xF1);
|
||||
OLED_WriteCommand(0xDB); //设置VCOMH取消选择级别
|
||||
OLED_WriteCommand(0x30);
|
||||
OLED_WriteCommand(0xA4); //设置整个显示打开/关闭
|
||||
OLED_WriteCommand(0xA6); //设置正常/倒转显示
|
||||
OLED_WriteCommand(0x8D); //设置充电泵
|
||||
OLED_WriteCommand(0x14);
|
||||
OLED_WriteCommand(0xAF); //开启显示
|
||||
|
||||
OLED_Clear();
|
||||
}
|
||||
@@ -0,0 +1,21 @@
|
||||
// ======================================================
|
||||
// OLED.h (最终修正版)
|
||||
// ======================================================
|
||||
#ifndef __OLED_H
|
||||
#define __OLED_H
|
||||
|
||||
#include "stm32f10x.h"
|
||||
|
||||
void OLED_Init(void);
|
||||
void OLED_Clear(void);
|
||||
void OLED_ShowChar(uint8_t Line, uint8_t Column, char Char);
|
||||
void OLED_ShowString(uint8_t Line, uint8_t Column, char *String);
|
||||
void OLED_ShowNum(uint8_t Line, uint8_t Column, uint32_t Number, uint8_t Length);
|
||||
void OLED_ShowSignedNum(uint8_t Line, uint8_t Column, int32_t Number, uint8_t Length);
|
||||
void OLED_ShowHexNum(uint8_t Line, uint8_t Column, uint32_t Number, uint8_t Length);
|
||||
void OLED_ShowBinNum(uint8_t Line, uint8_t Column, uint32_t Number, uint8_t Length);
|
||||
|
||||
// 添加显示汉字的函数声明
|
||||
void OLED_ShowChinese(uint8_t Line, uint8_t Column, uint8_t num);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,326 @@
|
||||
#ifndef __OLED_FONT_H
|
||||
#define __OLED_FONT_H
|
||||
|
||||
/*OLED字模库，宽8像素，高16像素*/
|
||||
const uint8_t OLED_F8x16[][16]=
|
||||
{
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,// 0
|
||||
|
||||
0x00,0x00,0x00,0xF8,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x33,0x30,0x00,0x00,0x00,//! 1
|
||||
|
||||
0x00,0x10,0x0C,0x06,0x10,0x0C,0x06,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//" 2
|
||||
|
||||
0x40,0xC0,0x78,0x40,0xC0,0x78,0x40,0x00,
|
||||
0x04,0x3F,0x04,0x04,0x3F,0x04,0x04,0x00,//# 3
|
||||
|
||||
0x00,0x70,0x88,0xFC,0x08,0x30,0x00,0x00,
|
||||
0x00,0x18,0x20,0xFF,0x21,0x1E,0x00,0x00,//$ 4
|
||||
|
||||
0xF0,0x08,0xF0,0x00,0xE0,0x18,0x00,0x00,
|
||||
0x00,0x21,0x1C,0x03,0x1E,0x21,0x1E,0x00,//% 5
|
||||
|
||||
0x00,0xF0,0x08,0x88,0x70,0x00,0x00,0x00,
|
||||
0x1E,0x21,0x23,0x24,0x19,0x27,0x21,0x10,//& 6
|
||||
|
||||
0x10,0x16,0x0E,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//' 7
|
||||
|
||||
0x00,0x00,0x00,0xE0,0x18,0x04,0x02,0x00,
|
||||
0x00,0x00,0x00,0x07,0x18,0x20,0x40,0x00,//( 8
|
||||
|
||||
0x00,0x02,0x04,0x18,0xE0,0x00,0x00,0x00,
|
||||
0x00,0x40,0x20,0x18,0x07,0x00,0x00,0x00,//) 9
|
||||
|
||||
0x40,0x40,0x80,0xF0,0x80,0x40,0x40,0x00,
|
||||
0x02,0x02,0x01,0x0F,0x01,0x02,0x02,0x00,//* 10
|
||||
|
||||
0x00,0x00,0x00,0xF0,0x00,0x00,0x00,0x00,
|
||||
0x01,0x01,0x01,0x1F,0x01,0x01,0x01,0x00,//+ 11
|
||||
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x80,0xB0,0x70,0x00,0x00,0x00,0x00,0x00,//, 12
|
||||
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//- 13
|
||||
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x30,0x30,0x00,0x00,0x00,0x00,0x00,//. 14
|
||||
|
||||
0x00,0x00,0x00,0x00,0x80,0x60,0x18,0x04,
|
||||
0x00,0x60,0x18,0x06,0x01,0x00,0x00,0x00,/// 15
|
||||
|
||||
0x00,0xE0,0x10,0x08,0x08,0x10,0xE0,0x00,
|
||||
0x00,0x0F,0x10,0x20,0x20,0x10,0x0F,0x00,//0 16
|
||||
|
||||
0x00,0x10,0x10,0xF8,0x00,0x00,0x00,0x00,
|
||||
0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//1 17
|
||||
|
||||
0x00,0x70,0x08,0x08,0x08,0x88,0x70,0x00,
|
||||
0x00,0x30,0x28,0x24,0x22,0x21,0x30,0x00,//2 18
|
||||
|
||||
0x00,0x30,0x08,0x88,0x88,0x48,0x30,0x00,
|
||||
0x00,0x18,0x20,0x20,0x20,0x11,0x0E,0x00,//3 19
|
||||
|
||||
0x00,0x00,0xC0,0x20,0x10,0xF8,0x00,0x00,
|
||||
0x00,0x07,0x04,0x24,0x24,0x3F,0x24,0x00,//4 20
|
||||
|
||||
0x00,0xF8,0x08,0x88,0x88,0x08,0x08,0x00,
|
||||
0x00,0x19,0x21,0x20,0x20,0x11,0x0E,0x00,//5 21
|
||||
|
||||
0x00,0xE0,0x10,0x88,0x88,0x18,0x00,0x00,
|
||||
0x00,0x0F,0x11,0x20,0x20,0x11,0x0E,0x00,//6 22
|
||||
|
||||
0x00,0x38,0x08,0x08,0xC8,0x38,0x08,0x00,
|
||||
0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,//7 23
|
||||
|
||||
0x00,0x70,0x88,0x08,0x08,0x88,0x70,0x00,
|
||||
0x00,0x1C,0x22,0x21,0x21,0x22,0x1C,0x00,//8 24
|
||||
|
||||
0x00,0xE0,0x10,0x08,0x08,0x10,0xE0,0x00,
|
||||
0x00,0x00,0x31,0x22,0x22,0x11,0x0F,0x00,//9 25
|
||||
|
||||
0x00,0x00,0x00,0xC0,0xC0,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x30,0x30,0x00,0x00,0x00,//: 26
|
||||
|
||||
0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x80,0x60,0x00,0x00,0x00,0x00,//; 27
|
||||
|
||||
0x00,0x00,0x80,0x40,0x20,0x10,0x08,0x00,
|
||||
0x00,0x01,0x02,0x04,0x08,0x10,0x20,0x00,//< 28
|
||||
|
||||
0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x00,
|
||||
0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x00,//= 29
|
||||
|
||||
0x00,0x08,0x10,0x20,0x40,0x80,0x00,0x00,
|
||||
0x00,0x20,0x10,0x08,0x04,0x02,0x01,0x00,//> 30
|
||||
|
||||
0x00,0x70,0x48,0x08,0x08,0x08,0xF0,0x00,
|
||||
0x00,0x00,0x00,0x30,0x36,0x01,0x00,0x00,//? 31
|
||||
|
||||
0xC0,0x30,0xC8,0x28,0xE8,0x10,0xE0,0x00,
|
||||
0x07,0x18,0x27,0x24,0x23,0x14,0x0B,0x00,//@ 32
|
||||
|
||||
0x00,0x00,0xC0,0x38,0xE0,0x00,0x00,0x00,
|
||||
0x20,0x3C,0x23,0x02,0x02,0x27,0x38,0x20,//A 33
|
||||
|
||||
0x08,0xF8,0x88,0x88,0x88,0x70,0x00,0x00,
|
||||
0x20,0x3F,0x20,0x20,0x20,0x11,0x0E,0x00,//B 34
|
||||
|
||||
0xC0,0x30,0x08,0x08,0x08,0x08,0x38,0x00,
|
||||
0x07,0x18,0x20,0x20,0x20,0x10,0x08,0x00,//C 35
|
||||
|
||||
0x08,0xF8,0x08,0x08,0x08,0x10,0xE0,0x00,
|
||||
0x20,0x3F,0x20,0x20,0x20,0x10,0x0F,0x00,//D 36
|
||||
|
||||
0x08,0xF8,0x88,0x88,0xE8,0x08,0x10,0x00,
|
||||
0x20,0x3F,0x20,0x20,0x23,0x20,0x18,0x00,//E 37
|
||||
|
||||
0x08,0xF8,0x88,0x88,0xE8,0x08,0x10,0x00,
|
||||
0x20,0x3F,0x20,0x00,0x03,0x00,0x00,0x00,//F 38
|
||||
|
||||
0xC0,0x30,0x08,0x08,0x08,0x38,0x00,0x00,
|
||||
0x07,0x18,0x20,0x20,0x22,0x1E,0x02,0x00,//G 39
|
||||
|
||||
0x08,0xF8,0x08,0x00,0x00,0x08,0xF8,0x08,
|
||||
0x20,0x3F,0x21,0x01,0x01,0x21,0x3F,0x20,//H 40
|
||||
|
||||
0x00,0x08,0x08,0xF8,0x08,0x08,0x00,0x00,
|
||||
0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//I 41
|
||||
|
||||
0x00,0x00,0x08,0x08,0xF8,0x08,0x08,0x00,
|
||||
0xC0,0x80,0x80,0x80,0x7F,0x00,0x00,0x00,//J 42
|
||||
|
||||
0x08,0xF8,0x88,0xC0,0x28,0x18,0x08,0x00,
|
||||
0x20,0x3F,0x20,0x01,0x26,0x38,0x20,0x00,//K 43
|
||||
|
||||
0x08,0xF8,0x08,0x00,0x00,0x00,0x00,0x00,
|
||||
0x20,0x3F,0x20,0x20,0x20,0x20,0x30,0x00,//L 44
|
||||
|
||||
0x08,0xF8,0xF8,0x00,0xF8,0xF8,0x08,0x00,
|
||||
0x20,0x3F,0x00,0x3F,0x00,0x3F,0x20,0x00,//M 45
|
||||
|
||||
0x08,0xF8,0x30,0xC0,0x00,0x08,0xF8,0x08,
|
||||
0x20,0x3F,0x20,0x00,0x07,0x18,0x3F,0x00,//N 46
|
||||
|
||||
0xE0,0x10,0x08,0x08,0x08,0x10,0xE0,0x00,
|
||||
0x0F,0x10,0x20,0x20,0x20,0x10,0x0F,0x00,//O 47
|
||||
|
||||
0x08,0xF8,0x08,0x08,0x08,0x08,0xF0,0x00,
|
||||
0x20,0x3F,0x21,0x01,0x01,0x01,0x00,0x00,//P 48
|
||||
|
||||
0xE0,0x10,0x08,0x08,0x08,0x10,0xE0,0x00,
|
||||
0x0F,0x18,0x24,0x24,0x38,0x50,0x4F,0x00,//Q 49
|
||||
|
||||
0x08,0xF8,0x88,0x88,0x88,0x88,0x70,0x00,
|
||||
0x20,0x3F,0x20,0x00,0x03,0x0C,0x30,0x20,//R 50
|
||||
|
||||
0x00,0x70,0x88,0x08,0x08,0x08,0x38,0x00,
|
||||
0x00,0x38,0x20,0x21,0x21,0x22,0x1C,0x00,//S 51
|
||||
|
||||
0x18,0x08,0x08,0xF8,0x08,0x08,0x18,0x00,
|
||||
0x00,0x00,0x20,0x3F,0x20,0x00,0x00,0x00,//T 52
|
||||
|
||||
0x08,0xF8,0x08,0x00,0x00,0x08,0xF8,0x08,
|
||||
0x00,0x1F,0x20,0x20,0x20,0x20,0x1F,0x00,//U 53
|
||||
|
||||
0x08,0x78,0x88,0x00,0x00,0xC8,0x38,0x08,
|
||||
0x00,0x00,0x07,0x38,0x0E,0x01,0x00,0x00,//V 54
|
||||
|
||||
0xF8,0x08,0x00,0xF8,0x00,0x08,0xF8,0x00,
|
||||
0x03,0x3C,0x07,0x00,0x07,0x3C,0x03,0x00,//W 55
|
||||
|
||||
0x08,0x18,0x68,0x80,0x80,0x68,0x18,0x08,
|
||||
0x20,0x30,0x2C,0x03,0x03,0x2C,0x30,0x20,//X 56
|
||||
|
||||
0x08,0x38,0xC8,0x00,0xC8,0x38,0x08,0x00,
|
||||
0x00,0x00,0x20,0x3F,0x20,0x00,0x00,0x00,//Y 57
|
||||
|
||||
0x10,0x08,0x08,0x08,0xC8,0x38,0x08,0x00,
|
||||
0x20,0x38,0x26,0x21,0x20,0x20,0x18,0x00,//Z 58
|
||||
|
||||
0x00,0x00,0x00,0xFE,0x02,0x02,0x02,0x00,
|
||||
0x00,0x00,0x00,0x7F,0x40,0x40,0x40,0x00,//[ 59
|
||||
|
||||
0x00,0x0C,0x30,0xC0,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x01,0x06,0x38,0xC0,0x00,//\ 60
|
||||
|
||||
0x00,0x02,0x02,0x02,0xFE,0x00,0x00,0x00,
|
||||
0x00,0x40,0x40,0x40,0x7F,0x00,0x00,0x00,//] 61
|
||||
|
||||
0x00,0x00,0x04,0x02,0x02,0x02,0x04,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//^ 62
|
||||
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,//_ 63
|
||||
|
||||
0x00,0x02,0x02,0x04,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//` 64
|
||||
|
||||
0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,
|
||||
0x00,0x19,0x24,0x22,0x22,0x22,0x3F,0x20,//a 65
|
||||
|
||||
0x08,0xF8,0x00,0x80,0x80,0x00,0x00,0x00,
|
||||
0x00,0x3F,0x11,0x20,0x20,0x11,0x0E,0x00,//b 66
|
||||
|
||||
0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,
|
||||
0x00,0x0E,0x11,0x20,0x20,0x20,0x11,0x00,//c 67
|
||||
|
||||
0x00,0x00,0x00,0x80,0x80,0x88,0xF8,0x00,
|
||||
0x00,0x0E,0x11,0x20,0x20,0x10,0x3F,0x20,//d 68
|
||||
|
||||
0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,
|
||||
0x00,0x1F,0x22,0x22,0x22,0x22,0x13,0x00,//e 69
|
||||
|
||||
0x00,0x80,0x80,0xF0,0x88,0x88,0x88,0x18,
|
||||
0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//f 70
|
||||
|
||||
0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x00,
|
||||
0x00,0x6B,0x94,0x94,0x94,0x93,0x60,0x00,//g 71
|
||||
|
||||
0x08,0xF8,0x00,0x80,0x80,0x80,0x00,0x00,
|
||||
0x20,0x3F,0x21,0x00,0x00,0x20,0x3F,0x20,//h 72
|
||||
|
||||
0x00,0x80,0x98,0x98,0x00,0x00,0x00,0x00,
|
||||
0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//i 73
|
||||
|
||||
0x00,0x00,0x00,0x80,0x98,0x98,0x00,0x00,
|
||||
0x00,0xC0,0x80,0x80,0x80,0x7F,0x00,0x00,//j 74
|
||||
|
||||
0x08,0xF8,0x00,0x00,0x80,0x80,0x80,0x00,
|
||||
0x20,0x3F,0x24,0x02,0x2D,0x30,0x20,0x00,//k 75
|
||||
|
||||
0x00,0x08,0x08,0xF8,0x00,0x00,0x00,0x00,
|
||||
0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//l 76
|
||||
|
||||
0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00,
|
||||
0x20,0x3F,0x20,0x00,0x3F,0x20,0x00,0x3F,//m 77
|
||||
|
||||
0x80,0x80,0x00,0x80,0x80,0x80,0x00,0x00,
|
||||
0x20,0x3F,0x21,0x00,0x00,0x20,0x3F,0x20,//n 78
|
||||
|
||||
0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,
|
||||
0x00,0x1F,0x20,0x20,0x20,0x20,0x1F,0x00,//o 79
|
||||
|
||||
0x80,0x80,0x00,0x80,0x80,0x00,0x00,0x00,
|
||||
0x80,0xFF,0xA1,0x20,0x20,0x11,0x0E,0x00,//p 80
|
||||
|
||||
0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x00,
|
||||
0x00,0x0E,0x11,0x20,0x20,0xA0,0xFF,0x80,//q 81
|
||||
|
||||
0x80,0x80,0x80,0x00,0x80,0x80,0x80,0x00,
|
||||
0x20,0x20,0x3F,0x21,0x20,0x00,0x01,0x00,//r 82
|
||||
|
||||
0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x00,
|
||||
0x00,0x33,0x24,0x24,0x24,0x24,0x19,0x00,//s 83
|
||||
|
||||
0x00,0x80,0x80,0xE0,0x80,0x80,0x00,0x00,
|
||||
0x00,0x00,0x00,0x1F,0x20,0x20,0x00,0x00,//t 84
|
||||
|
||||
0x80,0x80,0x00,0x00,0x00,0x80,0x80,0x00,
|
||||
0x00,0x1F,0x20,0x20,0x20,0x10,0x3F,0x20,//u 85
|
||||
|
||||
0x80,0x80,0x80,0x00,0x00,0x80,0x80,0x80,
|
||||
0x00,0x01,0x0E,0x30,0x08,0x06,0x01,0x00,//v 86
|
||||
|
||||
0x80,0x80,0x00,0x80,0x00,0x80,0x80,0x80,
|
||||
0x0F,0x30,0x0C,0x03,0x0C,0x30,0x0F,0x00,//w 87
|
||||
|
||||
0x00,0x80,0x80,0x00,0x80,0x80,0x80,0x00,
|
||||
0x00,0x20,0x31,0x2E,0x0E,0x31,0x20,0x00,//x 88
|
||||
|
||||
0x80,0x80,0x80,0x00,0x00,0x80,0x80,0x80,
|
||||
0x80,0x81,0x8E,0x70,0x18,0x06,0x01,0x00,//y 89
|
||||
|
||||
0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x00,
|
||||
0x00,0x21,0x30,0x2C,0x22,0x21,0x30,0x00,//z 90
|
||||
|
||||
0x00,0x00,0x00,0x00,0x80,0x7C,0x02,0x02,
|
||||
0x00,0x00,0x00,0x00,0x00,0x3F,0x40,0x40,//{ 91
|
||||
|
||||
0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,//| 92
|
||||
|
||||
0x00,0x02,0x02,0x7C,0x80,0x00,0x00,0x00,
|
||||
0x00,0x40,0x40,0x3F,0x00,0x00,0x00,0x00,//} 93
|
||||
|
||||
0x00,0x06,0x01,0x01,0x02,0x02,0x04,0x04,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//~ 94
|
||||
};
|
||||
|
||||
/*
|
||||
* 添加16x16中文字模库
|
||||
* 每个汉字占用32个字节
|
||||
* 汉字列表: 成(0) 功(1) 识(2) 别(3) 录(4) 入(5) 失(6) 败(7)
|
||||
*/
|
||||
const uint8_t OLED_F16x16_CN[][32]=
|
||||
{
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x3F,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x80,0x40,0x20,0x10,0x0C,0x03,0x00,0x00,0x00,0x03,0x0C,0x10,0x20,0x40,0x80,0x00},/*"成",0*/
|
||||
|
||||
{0x00,0xFE,0x22,0x22,0xFE,0x00,0x40,0x20,0x50,0x4C,0x43,0x4C,0x50,0x20,0x40,0x00,
|
||||
0x80,0x7F,0x02,0x82,0xFF,0x00,0x40,0x44,0x58,0x41,0x4E,0x60,0x58,0x47,0x40,0x00},/*"功",1*/
|
||||
|
||||
{0x40,0x40,0x42,0xCC,0x00,0x00,0x00,0xFC,0x04,0x04,0x04,0x04,0x04,0xFC,0x00,0x00,
|
||||
0x00,0x00,0x00,0x3F,0x10,0x88,0x40,0x23,0x19,0x01,0x01,0x09,0x11,0x23,0xC0,0x00},/*"识",2*/
|
||||
|
||||
{0x00,0x3E,0x22,0xE2,0x22,0x22,0x22,0x3E,0x00,0x00,0xF8,0x00,0x00,0xFF,0x00,0x00,
|
||||
0x81,0x41,0x31,0x0F,0x41,0x81,0x41,0x3F,0x00,0x00,0x0F,0x40,0x80,0x7F,0x00,0x00},/*"别",3*/
|
||||
|
||||
{0x00,0x00,0xF8,0x88,0x88,0x88,0x88,0x08,0x08,0xFF,0x08,0x09,0x0A,0xC8,0x08,0x00,
|
||||
0x80,0x60,0x1F,0x00,0x10,0x20,0x1F,0x80,0x40,0x21,0x16,0x18,0x26,0x41,0xF8,0x00},/*"录",4*/
|
||||
|
||||
{0x08,0x08,0x08,0xF8,0x08,0x08,0x08,0x10,0x10,0xFF,0x10,0x10,0x10,0xF0,0x00,0x00,
|
||||
0x10,0x30,0x10,0x1F,0x08,0x88,0x48,0x30,0x0E,0x01,0x40,0x80,0x40,0x3F,0x00,0x00},/*"入",5*/
|
||||
|
||||
{0x00,0x40,0x30,0x1E,0x10,0x10,0x10,0xFF,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00,
|
||||
0x81,0x81,0x41,0x21,0x11,0x0D,0x03,0x01,0x03,0x0D,0x11,0x21,0x41,0x81,0x81,0x00},/*"失",6*/
|
||||
|
||||
{0x00,0xFE,0x02,0xFA,0x02,0xFE,0x40,0x20,0xD8,0x17,0x10,0x10,0xF0,0x10,0x10,0x00,
|
||||
0x80,0x47,0x30,0x0F,0x10,0x67,0x80,0x40,0x21,0x16,0x08,0x16,0x21,0x40,0x80,0x00},/*"败",7*/
|
||||
};
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,83 @@
|
||||
#include "Serial.h"
|
||||
#include "Delay.h" // Get_Time_ms 在这里，所以我们包含它
|
||||
#include <string.h>
|
||||
|
||||
#define RX_BUFFER_SIZE 1024 // ← 增大到1024字节，支持完整HTTP响应
|
||||
char RxBuffer[RX_BUFFER_SIZE];
|
||||
uint16_t RxCounter = 0;
|
||||
|
||||
// 初始化ESP8266所用的串口 (根据连接图.md: USART1 PA9/PA10)
|
||||
void Serial_Init(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
USART_InitTypeDef USART_InitStructure;
|
||||
NVIC_InitTypeDef NVIC_InitStructure;
|
||||
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_USART1, ENABLE);
|
||||
|
||||
// PA9: USART1_TX
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
|
||||
// PA10: USART1_RX
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
|
||||
USART_InitStructure.USART_BaudRate = 115200;
|
||||
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
|
||||
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
||||
USART_InitStructure.USART_Parity = USART_Parity_No;
|
||||
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||
USART_Init(USART1, &USART_InitStructure);
|
||||
|
||||
USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);
|
||||
|
||||
NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; // 优先级低于K210
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
|
||||
USART_Cmd(USART1, ENABLE);
|
||||
}
|
||||
|
||||
// 发送字符串
|
||||
void Serial_SendString(const char* String)
|
||||
{
|
||||
for (uint32_t i = 0; String[i] != '\0'; i++)
|
||||
{
|
||||
while (USART_GetFlagStatus(USART1, USART_FLAG_TXE) == RESET);
|
||||
USART_SendData(USART1, String[i]);
|
||||
}
|
||||
}
|
||||
|
||||
// 获取接收缓冲区
|
||||
char* Serial_GetRxBuffer(void)
|
||||
{
|
||||
return RxBuffer;
|
||||
}
|
||||
|
||||
// 清空接收缓冲区
|
||||
void Serial_ClearRxBuffer(void)
|
||||
{
|
||||
memset(RxBuffer, 0, RX_BUFFER_SIZE);
|
||||
RxCounter = 0;
|
||||
}
|
||||
|
||||
// USART1中断服务函数 (ESP8266)
|
||||
void USART1_IRQHandler(void)
|
||||
{
|
||||
if (USART_GetITStatus(USART1, USART_IT_RXNE) == SET)
|
||||
{
|
||||
uint8_t RxData = USART_ReceiveData(USART1);
|
||||
if (RxCounter < RX_BUFFER_SIZE - 1)
|
||||
{
|
||||
RxBuffer[RxCounter++] = RxData;
|
||||
}
|
||||
USART_ClearITPendingBit(USART1, USART_IT_RXNE);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,17 @@
|
||||
#ifndef __SERIAL_H
|
||||
#define __SERIAL_H
|
||||
|
||||
#include <stdio.h>
|
||||
#include "stm32f10x.h"
|
||||
|
||||
void Serial_Init(void); // 初始化串口
|
||||
void Serial_SendByte(uint8_t Byte); // 发送一个字节
|
||||
void Serial_SendString(const char* String); // 发送字符串
|
||||
char* Serial_GetRxBuffer(void); // 获取接收缓冲区指针
|
||||
void Serial_ClearRxBuffer(void); // 清空接收缓冲区
|
||||
|
||||
// 注意：Get_Time_ms() 函数与串口无关，应该在 `Delay.h` 中声明。
|
||||
// 我们暂时将它与串口放一起，但更规范的做法是分离。
|
||||
uint32_t Get_Time_ms(void);
|
||||
|
||||
#endif
|
||||
+237
@@ -0,0 +1,237 @@
|
||||
/*
|
||||
* 标准AES-128-CBC实现 - 与OpenSSL完全兼容
|
||||
* 基于FIPS-197标准
|
||||
*/
|
||||
|
||||
#include "aes.h"
|
||||
#include <string.h>
|
||||
|
||||
// S-box
|
||||
static const uint8_t sbox[256] = {
|
||||
0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76,
|
||||
0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0,
|
||||
0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15,
|
||||
0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75,
|
||||
0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84,
|
||||
0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf,
|
||||
0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8,
|
||||
0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2,
|
||||
0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73,
|
||||
0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb,
|
||||
0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79,
|
||||
0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08,
|
||||
0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a,
|
||||
0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e,
|
||||
0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf,
|
||||
0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
|
||||
};
|
||||
|
||||
// Rcon
|
||||
static const uint8_t Rcon[11] = {
|
||||
0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36
|
||||
};
|
||||
|
||||
#define getSBoxValue(num) (sbox[(num)])
|
||||
|
||||
// 密钥扩展
|
||||
static void KeyExpansion(uint8_t* RoundKey, const uint8_t* Key)
|
||||
{
|
||||
unsigned i, j, k;
|
||||
uint8_t tempa[4];
|
||||
|
||||
// 前4个轮密钥直接复制
|
||||
for (i = 0; i < 4; ++i) {
|
||||
RoundKey[(i * 4) + 0] = Key[(i * 4) + 0];
|
||||
RoundKey[(i * 4) + 1] = Key[(i * 4) + 1];
|
||||
RoundKey[(i * 4) + 2] = Key[(i * 4) + 2];
|
||||
RoundKey[(i * 4) + 3] = Key[(i * 4) + 3];
|
||||
}
|
||||
|
||||
// 生成其余轮密钥
|
||||
for (i = 4; i < 44; ++i) {
|
||||
k = (i - 1) * 4;
|
||||
tempa[0] = RoundKey[k + 0];
|
||||
tempa[1] = RoundKey[k + 1];
|
||||
tempa[2] = RoundKey[k + 2];
|
||||
tempa[3] = RoundKey[k + 3];
|
||||
|
||||
if (i % 4 == 0) {
|
||||
// RotWord
|
||||
const uint8_t u8tmp = tempa[0];
|
||||
tempa[0] = tempa[1];
|
||||
tempa[1] = tempa[2];
|
||||
tempa[2] = tempa[3];
|
||||
tempa[3] = u8tmp;
|
||||
|
||||
// SubWord
|
||||
tempa[0] = getSBoxValue(tempa[0]);
|
||||
tempa[1] = getSBoxValue(tempa[1]);
|
||||
tempa[2] = getSBoxValue(tempa[2]);
|
||||
tempa[3] = getSBoxValue(tempa[3]);
|
||||
|
||||
tempa[0] = tempa[0] ^ Rcon[i / 4];
|
||||
}
|
||||
|
||||
j = i * 4;
|
||||
k = (i - 4) * 4;
|
||||
RoundKey[j + 0] = RoundKey[k + 0] ^ tempa[0];
|
||||
RoundKey[j + 1] = RoundKey[k + 1] ^ tempa[1];
|
||||
RoundKey[j + 2] = RoundKey[k + 2] ^ tempa[2];
|
||||
RoundKey[j + 3] = RoundKey[k + 3] ^ tempa[3];
|
||||
}
|
||||
}
|
||||
|
||||
// AddRoundKey
|
||||
static void AddRoundKey(uint8_t round, uint8_t* state, const uint8_t* RoundKey)
|
||||
{
|
||||
uint8_t i, j;
|
||||
for (i = 0; i < 4; ++i) {
|
||||
for (j = 0; j < 4; ++j) {
|
||||
state[i * 4 + j] ^= RoundKey[(round * 16) + (i * 4 + j)];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// SubBytes
|
||||
static void SubBytes(uint8_t* state)
|
||||
{
|
||||
uint8_t i;
|
||||
for (i = 0; i < 16; ++i) {
|
||||
state[i] = getSBoxValue(state[i]);
|
||||
}
|
||||
}
|
||||
|
||||
// ShiftRows
|
||||
static void ShiftRows(uint8_t* state)
|
||||
{
|
||||
uint8_t temp;
|
||||
|
||||
// 第二行左移1字节
|
||||
temp = state[1];
|
||||
state[1] = state[5];
|
||||
state[5] = state[9];
|
||||
state[9] = state[13];
|
||||
state[13] = temp;
|
||||
|
||||
// 第三行左移2字节
|
||||
temp = state[2];
|
||||
state[2] = state[10];
|
||||
state[10] = temp;
|
||||
temp = state[6];
|
||||
state[6] = state[14];
|
||||
state[14] = temp;
|
||||
|
||||
// 第四行左移3字节
|
||||
temp = state[15];
|
||||
state[15] = state[11];
|
||||
state[11] = state[7];
|
||||
state[7] = state[3];
|
||||
state[3] = temp;
|
||||
}
|
||||
|
||||
// xtime (用于MixColumns)
|
||||
static uint8_t xtime(uint8_t x)
|
||||
{
|
||||
return ((x << 1) ^ (((x >> 7) & 1) * 0x1b));
|
||||
}
|
||||
|
||||
// MixColumns
|
||||
static void MixColumns(uint8_t* state)
|
||||
{
|
||||
uint8_t i;
|
||||
uint8_t Tmp, Tm, t;
|
||||
|
||||
for (i = 0; i < 4; ++i) {
|
||||
t = state[i * 4 + 0];
|
||||
Tmp = state[i * 4 + 0] ^ state[i * 4 + 1] ^ state[i * 4 + 2] ^ state[i * 4 + 3];
|
||||
|
||||
Tm = state[i * 4 + 0] ^ state[i * 4 + 1];
|
||||
Tm = xtime(Tm);
|
||||
state[i * 4 + 0] ^= Tm ^ Tmp;
|
||||
|
||||
Tm = state[i * 4 + 1] ^ state[i * 4 + 2];
|
||||
Tm = xtime(Tm);
|
||||
state[i * 4 + 1] ^= Tm ^ Tmp;
|
||||
|
||||
Tm = state[i * 4 + 2] ^ state[i * 4 + 3];
|
||||
Tm = xtime(Tm);
|
||||
state[i * 4 + 2] ^= Tm ^ Tmp;
|
||||
|
||||
Tm = state[i * 4 + 3] ^ t;
|
||||
Tm = xtime(Tm);
|
||||
state[i * 4 + 3] ^= Tm ^ Tmp;
|
||||
}
|
||||
}
|
||||
|
||||
// Cipher - AES加密核心
|
||||
static void Cipher(uint8_t* state, const uint8_t* RoundKey)
|
||||
{
|
||||
uint8_t round = 0;
|
||||
|
||||
// 初始轮密钥加
|
||||
AddRoundKey(0, state, RoundKey);
|
||||
|
||||
// 9轮标准变换
|
||||
for (round = 1; round < 10; ++round) {
|
||||
SubBytes(state);
|
||||
ShiftRows(state);
|
||||
MixColumns(state);
|
||||
AddRoundKey(round, state, RoundKey);
|
||||
}
|
||||
|
||||
// 最后一轮（无MixColumns）
|
||||
SubBytes(state);
|
||||
ShiftRows(state);
|
||||
AddRoundKey(10, state, RoundKey);
|
||||
}
|
||||
|
||||
// ========== 公开API函数 ==========
|
||||
|
||||
void AES_init_ctx(struct AES_ctx* ctx, const uint8_t* key)
|
||||
{
|
||||
KeyExpansion(ctx->RoundKey, key);
|
||||
}
|
||||
|
||||
void AES_init_ctx_iv(struct AES_ctx* ctx, const uint8_t* key, const uint8_t* iv)
|
||||
{
|
||||
KeyExpansion(ctx->RoundKey, key);
|
||||
memcpy(ctx->Iv, iv, AES_BLOCKLEN);
|
||||
}
|
||||
|
||||
void AES_ECB_encrypt(const struct AES_ctx* ctx, uint8_t* buf)
|
||||
{
|
||||
Cipher(buf, ctx->RoundKey);
|
||||
}
|
||||
|
||||
void AES_CBC_encrypt_buffer(struct AES_ctx* ctx, uint8_t* buf, size_t length)
|
||||
{
|
||||
size_t i;
|
||||
uint8_t j;
|
||||
|
||||
for (i = 0; i < length; i += AES_BLOCKLEN) {
|
||||
// XOR with IV/previous ciphertext block
|
||||
for (j = 0; j < AES_BLOCKLEN; ++j) {
|
||||
buf[i + j] ^= ctx->Iv[j];
|
||||
}
|
||||
|
||||
// Encrypt block
|
||||
Cipher(buf + i, ctx->RoundKey);
|
||||
|
||||
// Update IV to current ciphertext block
|
||||
memcpy(ctx->Iv, buf + i, AES_BLOCKLEN);
|
||||
}
|
||||
}
|
||||
|
||||
// STM32端不需要解密功能
|
||||
void AES_ECB_decrypt(const struct AES_ctx* ctx, uint8_t* buf)
|
||||
{
|
||||
(void)ctx;
|
||||
(void)buf;
|
||||
}
|
||||
|
||||
void AES_CBC_decrypt_buffer(struct AES_ctx* ctx, uint8_t* buf, size_t length)
|
||||
{
|
||||
(void)ctx;
|
||||
(void)buf;
|
||||
(void)length;
|
||||
}
|
||||
@@ -0,0 +1,65 @@
|
||||
#ifndef _AES_H_
|
||||
#define _AES_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
|
||||
// 使用AES-128（16字节密钥）
|
||||
#define AES_BLOCKLEN 16 // Block length in bytes - AES is 128b block only
|
||||
#define AES_KEYLEN 16 // Key length in bytes (AES-128)
|
||||
#define AES_keyExpSize 176
|
||||
|
||||
struct AES_ctx
|
||||
{
|
||||
uint8_t RoundKey[AES_keyExpSize];
|
||||
uint8_t Iv[AES_BLOCKLEN]; // 独立的IV存储（标准做法，与OpenSSL兼容）
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief 初始化AES上下文
|
||||
* @param ctx AES上下文结构
|
||||
* @param key 16字节密钥
|
||||
*/
|
||||
void AES_init_ctx(struct AES_ctx* ctx, const uint8_t* key);
|
||||
|
||||
/**
|
||||
* @brief AES-ECB加密（单个块）
|
||||
* @param ctx AES上下文
|
||||
* @param buf 要加密的数据（16字节块）
|
||||
*/
|
||||
void AES_ECB_encrypt(const struct AES_ctx* ctx, uint8_t* buf);
|
||||
|
||||
/**
|
||||
* @brief AES-ECB解密（单个块）
|
||||
* @param ctx AES上下文
|
||||
* @param buf 要解密的数据（16字节块）
|
||||
*/
|
||||
void AES_ECB_decrypt(const struct AES_ctx* ctx, uint8_t* buf);
|
||||
|
||||
/**
|
||||
* @brief AES-CBC加密（多个块）
|
||||
* @param ctx AES上下文
|
||||
* @param buf 要加密的数据
|
||||
* @param length 数据长度（必须是16的倍数）
|
||||
* @param iv 初始化向量（16字节）
|
||||
*/
|
||||
void AES_CBC_encrypt_buffer(struct AES_ctx* ctx, uint8_t* buf, size_t length);
|
||||
|
||||
/**
|
||||
* @brief AES-CBC解密（多个块）
|
||||
* @param ctx AES上下文
|
||||
* @param buf 要解密的数据
|
||||
* @param length 数据长度（必须是16的倍数）
|
||||
* @param iv 初始化向量（16字节）
|
||||
*/
|
||||
void AES_CBC_decrypt_buffer(struct AES_ctx* ctx, uint8_t* buf, size_t length);
|
||||
|
||||
/**
|
||||
* @brief 初始化AES上下文（CBC模式）
|
||||
* @param ctx AES上下文结构
|
||||
* @param key 16字节密钥
|
||||
* @param iv 16字节初始化向量
|
||||
*/
|
||||
void AES_init_ctx_iv(struct AES_ctx* ctx, const uint8_t* key, const uint8_t* iv);
|
||||
|
||||
#endif // _AES_H_
|
||||
@@ -0,0 +1,237 @@
|
||||
/*
|
||||
* 标准AES-128-CBC实现 - 与OpenSSL完全兼容
|
||||
* 基于FIPS-197标准
|
||||
*/
|
||||
|
||||
#include "aes.h"
|
||||
#include <string.h>
|
||||
|
||||
// S-box
|
||||
static const uint8_t sbox[256] = {
|
||||
0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76,
|
||||
0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0,
|
||||
0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15,
|
||||
0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75,
|
||||
0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84,
|
||||
0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf,
|
||||
0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8,
|
||||
0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2,
|
||||
0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73,
|
||||
0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb,
|
||||
0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79,
|
||||
0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08,
|
||||
0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a,
|
||||
0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e,
|
||||
0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf,
|
||||
0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
|
||||
};
|
||||
|
||||
// Rcon
|
||||
static const uint8_t Rcon[11] = {
|
||||
0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36
|
||||
};
|
||||
|
||||
#define getSBoxValue(num) (sbox[(num)])
|
||||
|
||||
// 密钥扩展
|
||||
static void KeyExpansion(uint8_t* RoundKey, const uint8_t* Key)
|
||||
{
|
||||
unsigned i, j, k;
|
||||
uint8_t tempa[4];
|
||||
|
||||
// 前4个轮密钥直接复制
|
||||
for (i = 0; i < 4; ++i) {
|
||||
RoundKey[(i * 4) + 0] = Key[(i * 4) + 0];
|
||||
RoundKey[(i * 4) + 1] = Key[(i * 4) + 1];
|
||||
RoundKey[(i * 4) + 2] = Key[(i * 4) + 2];
|
||||
RoundKey[(i * 4) + 3] = Key[(i * 4) + 3];
|
||||
}
|
||||
|
||||
// 生成其余轮密钥
|
||||
for (i = 4; i < 44; ++i) {
|
||||
k = (i - 1) * 4;
|
||||
tempa[0] = RoundKey[k + 0];
|
||||
tempa[1] = RoundKey[k + 1];
|
||||
tempa[2] = RoundKey[k + 2];
|
||||
tempa[3] = RoundKey[k + 3];
|
||||
|
||||
if (i % 4 == 0) {
|
||||
// RotWord
|
||||
const uint8_t u8tmp = tempa[0];
|
||||
tempa[0] = tempa[1];
|
||||
tempa[1] = tempa[2];
|
||||
tempa[2] = tempa[3];
|
||||
tempa[3] = u8tmp;
|
||||
|
||||
// SubWord
|
||||
tempa[0] = getSBoxValue(tempa[0]);
|
||||
tempa[1] = getSBoxValue(tempa[1]);
|
||||
tempa[2] = getSBoxValue(tempa[2]);
|
||||
tempa[3] = getSBoxValue(tempa[3]);
|
||||
|
||||
tempa[0] = tempa[0] ^ Rcon[i / 4];
|
||||
}
|
||||
|
||||
j = i * 4;
|
||||
k = (i - 4) * 4;
|
||||
RoundKey[j + 0] = RoundKey[k + 0] ^ tempa[0];
|
||||
RoundKey[j + 1] = RoundKey[k + 1] ^ tempa[1];
|
||||
RoundKey[j + 2] = RoundKey[k + 2] ^ tempa[2];
|
||||
RoundKey[j + 3] = RoundKey[k + 3] ^ tempa[3];
|
||||
}
|
||||
}
|
||||
|
||||
// AddRoundKey
|
||||
static void AddRoundKey(uint8_t round, uint8_t* state, const uint8_t* RoundKey)
|
||||
{
|
||||
uint8_t i, j;
|
||||
for (i = 0; i < 4; ++i) {
|
||||
for (j = 0; j < 4; ++j) {
|
||||
state[i * 4 + j] ^= RoundKey[(round * 16) + (i * 4 + j)];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// SubBytes
|
||||
static void SubBytes(uint8_t* state)
|
||||
{
|
||||
uint8_t i;
|
||||
for (i = 0; i < 16; ++i) {
|
||||
state[i] = getSBoxValue(state[i]);
|
||||
}
|
||||
}
|
||||
|
||||
// ShiftRows
|
||||
static void ShiftRows(uint8_t* state)
|
||||
{
|
||||
uint8_t temp;
|
||||
|
||||
// 第二行左移1字节
|
||||
temp = state[1];
|
||||
state[1] = state[5];
|
||||
state[5] = state[9];
|
||||
state[9] = state[13];
|
||||
state[13] = temp;
|
||||
|
||||
// 第三行左移2字节
|
||||
temp = state[2];
|
||||
state[2] = state[10];
|
||||
state[10] = temp;
|
||||
temp = state[6];
|
||||
state[6] = state[14];
|
||||
state[14] = temp;
|
||||
|
||||
// 第四行左移3字节
|
||||
temp = state[15];
|
||||
state[15] = state[11];
|
||||
state[11] = state[7];
|
||||
state[7] = state[3];
|
||||
state[3] = temp;
|
||||
}
|
||||
|
||||
// xtime (用于MixColumns)
|
||||
static uint8_t xtime(uint8_t x)
|
||||
{
|
||||
return ((x << 1) ^ (((x >> 7) & 1) * 0x1b));
|
||||
}
|
||||
|
||||
// MixColumns
|
||||
static void MixColumns(uint8_t* state)
|
||||
{
|
||||
uint8_t i;
|
||||
uint8_t Tmp, Tm, t;
|
||||
|
||||
for (i = 0; i < 4; ++i) {
|
||||
t = state[i * 4 + 0];
|
||||
Tmp = state[i * 4 + 0] ^ state[i * 4 + 1] ^ state[i * 4 + 2] ^ state[i * 4 + 3];
|
||||
|
||||
Tm = state[i * 4 + 0] ^ state[i * 4 + 1];
|
||||
Tm = xtime(Tm);
|
||||
state[i * 4 + 0] ^= Tm ^ Tmp;
|
||||
|
||||
Tm = state[i * 4 + 1] ^ state[i * 4 + 2];
|
||||
Tm = xtime(Tm);
|
||||
state[i * 4 + 1] ^= Tm ^ Tmp;
|
||||
|
||||
Tm = state[i * 4 + 2] ^ state[i * 4 + 3];
|
||||
Tm = xtime(Tm);
|
||||
state[i * 4 + 2] ^= Tm ^ Tmp;
|
||||
|
||||
Tm = state[i * 4 + 3] ^ t;
|
||||
Tm = xtime(Tm);
|
||||
state[i * 4 + 3] ^= Tm ^ Tmp;
|
||||
}
|
||||
}
|
||||
|
||||
// Cipher - AES加密核心
|
||||
static void Cipher(uint8_t* state, const uint8_t* RoundKey)
|
||||
{
|
||||
uint8_t round = 0;
|
||||
|
||||
// 初始轮密钥加
|
||||
AddRoundKey(0, state, RoundKey);
|
||||
|
||||
// 9轮标准变换
|
||||
for (round = 1; round < 10; ++round) {
|
||||
SubBytes(state);
|
||||
ShiftRows(state);
|
||||
MixColumns(state);
|
||||
AddRoundKey(round, state, RoundKey);
|
||||
}
|
||||
|
||||
// 最后一轮（无MixColumns）
|
||||
SubBytes(state);
|
||||
ShiftRows(state);
|
||||
AddRoundKey(10, state, RoundKey);
|
||||
}
|
||||
|
||||
// ========== 公开API函数 ==========
|
||||
|
||||
void AES_init_ctx(struct AES_ctx* ctx, const uint8_t* key)
|
||||
{
|
||||
KeyExpansion(ctx->RoundKey, key);
|
||||
}
|
||||
|
||||
void AES_init_ctx_iv(struct AES_ctx* ctx, const uint8_t* key, const uint8_t* iv)
|
||||
{
|
||||
KeyExpansion(ctx->RoundKey, key);
|
||||
memcpy(ctx->Iv, iv, AES_BLOCKLEN);
|
||||
}
|
||||
|
||||
void AES_ECB_encrypt(const struct AES_ctx* ctx, uint8_t* buf)
|
||||
{
|
||||
Cipher(buf, ctx->RoundKey);
|
||||
}
|
||||
|
||||
void AES_CBC_encrypt_buffer(struct AES_ctx* ctx, uint8_t* buf, size_t length)
|
||||
{
|
||||
size_t i;
|
||||
uint8_t j;
|
||||
|
||||
for (i = 0; i < length; i += AES_BLOCKLEN) {
|
||||
// XOR with IV/previous ciphertext block
|
||||
for (j = 0; j < AES_BLOCKLEN; ++j) {
|
||||
buf[i + j] ^= ctx->Iv[j];
|
||||
}
|
||||
|
||||
// Encrypt block
|
||||
Cipher(buf + i, ctx->RoundKey);
|
||||
|
||||
// Update IV to current ciphertext block
|
||||
memcpy(ctx->Iv, buf + i, AES_BLOCKLEN);
|
||||
}
|
||||
}
|
||||
|
||||
// STM32端不需要解密功能
|
||||
void AES_ECB_decrypt(const struct AES_ctx* ctx, uint8_t* buf)
|
||||
{
|
||||
(void)ctx;
|
||||
(void)buf;
|
||||
}
|
||||
|
||||
void AES_CBC_decrypt_buffer(struct AES_ctx* ctx, uint8_t* buf, size_t length)
|
||||
{
|
||||
(void)ctx;
|
||||
(void)buf;
|
||||
(void)length;
|
||||
}
|
||||
@@ -0,0 +1,63 @@
|
||||
#ifndef _AES_H_
|
||||
#define _AES_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
|
||||
// AES-128配置
|
||||
#define AES_BLOCKLEN 16 // Block length in bytes (AES is 128-bit block)
|
||||
#define AES_KEYLEN 16 // Key length in bytes (AES-128)
|
||||
#define AES_keyExpSize 176 // Expanded key size (44 * 4 bytes)
|
||||
|
||||
struct AES_ctx
|
||||
{
|
||||
uint8_t RoundKey[AES_keyExpSize]; // 扩展密钥
|
||||
uint8_t Iv[AES_BLOCKLEN]; // IV向量（独立存储，标准做法）
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief 初始化AES上下文（仅密钥）
|
||||
* @param ctx AES上下文结构
|
||||
* @param key 16字节密钥
|
||||
*/
|
||||
void AES_init_ctx(struct AES_ctx* ctx, const uint8_t* key);
|
||||
|
||||
/**
|
||||
* @brief 初始化AES上下文（密钥+IV）
|
||||
* @param ctx AES上下文结构
|
||||
* @param key 16字节密钥
|
||||
* @param iv 16字节初始化向量
|
||||
*/
|
||||
void AES_init_ctx_iv(struct AES_ctx* ctx, const uint8_t* key, const uint8_t* iv);
|
||||
|
||||
/**
|
||||
* @brief AES-ECB加密（单个块）
|
||||
* @param ctx AES上下文
|
||||
* @param buf 要加密的数据（16字节块）
|
||||
*/
|
||||
void AES_ECB_encrypt(const struct AES_ctx* ctx, uint8_t* buf);
|
||||
|
||||
/**
|
||||
* @brief AES-ECB解密（单个块）
|
||||
* @param ctx AES上下文
|
||||
* @param buf 要解密的数据（16字节块）
|
||||
*/
|
||||
void AES_ECB_decrypt(const struct AES_ctx* ctx, uint8_t* buf);
|
||||
|
||||
/**
|
||||
* @brief AES-CBC加密（多个块）
|
||||
* @param ctx AES上下文
|
||||
* @param buf 要加密的数据
|
||||
* @param length 数据长度（必须是16的倍数）
|
||||
*/
|
||||
void AES_CBC_encrypt_buffer(struct AES_ctx* ctx, uint8_t* buf, size_t length);
|
||||
|
||||
/**
|
||||
* @brief AES-CBC解密（多个块）
|
||||
* @param ctx AES上下文
|
||||
* @param buf 要解密的数据
|
||||
* @param length 数据长度（必须是16的倍数）
|
||||
*/
|
||||
void AES_CBC_decrypt_buffer(struct AES_ctx* ctx, uint8_t* buf, size_t length);
|
||||
|
||||
#endif // _AES_H_
|
||||
@@ -0,0 +1,81 @@
|
||||
/*
|
||||
* Base64 编码/解码实现
|
||||
* 优化用于嵌入式系统
|
||||
*/
|
||||
|
||||
#include "base64.h"
|
||||
#include <string.h>
|
||||
|
||||
static const char base64_chars[] =
|
||||
"ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+/";
|
||||
|
||||
uint32_t base64_encode(const uint8_t* input, uint32_t input_length, char* output)
|
||||
{
|
||||
uint32_t i, j;
|
||||
uint32_t output_length = 0;
|
||||
|
||||
for (i = 0, j = 0; i < input_length;) {
|
||||
uint32_t octet_a = i < input_length ? input[i++] : 0;
|
||||
uint32_t octet_b = i < input_length ? input[i++] : 0;
|
||||
uint32_t octet_c = i < input_length ? input[i++] : 0;
|
||||
|
||||
uint32_t triple = (octet_a << 16) + (octet_b << 8) + octet_c;
|
||||
|
||||
output[j++] = base64_chars[(triple >> 18) & 0x3F];
|
||||
output[j++] = base64_chars[(triple >> 12) & 0x3F];
|
||||
output[j++] = base64_chars[(triple >> 6) & 0x3F];
|
||||
output[j++] = base64_chars[triple & 0x3F];
|
||||
}
|
||||
|
||||
output_length = j;
|
||||
|
||||
// 处理padding
|
||||
uint32_t mod = input_length % 3;
|
||||
if (mod > 0) {
|
||||
for (i = 0; i < 3 - mod; i++) {
|
||||
output[output_length - 1 - i] = '=';
|
||||
}
|
||||
}
|
||||
|
||||
output[output_length] = '\0';
|
||||
return output_length;
|
||||
}
|
||||
|
||||
static uint8_t base64_char_value(char c)
|
||||
{
|
||||
if (c >= 'A' && c <= 'Z') return c - 'A';
|
||||
if (c >= 'a' && c <= 'z') return c - 'a' + 26;
|
||||
if (c >= '0' && c <= '9') return c - '0' + 52;
|
||||
if (c == '+') return 62;
|
||||
if (c == '/') return 63;
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint32_t base64_decode(const char* input, uint32_t input_length, uint8_t* output)
|
||||
{
|
||||
uint32_t i, j;
|
||||
uint32_t output_length = 0;
|
||||
|
||||
if (input_length % 4 != 0) return 0;
|
||||
|
||||
for (i = 0, j = 0; i < input_length;) {
|
||||
uint32_t sextet_a = input[i] == '=' ? 0 : base64_char_value(input[i]); i++;
|
||||
uint32_t sextet_b = input[i] == '=' ? 0 : base64_char_value(input[i]); i++;
|
||||
uint32_t sextet_c = input[i] == '=' ? 0 : base64_char_value(input[i]); i++;
|
||||
uint32_t sextet_d = input[i] == '=' ? 0 : base64_char_value(input[i]); i++;
|
||||
|
||||
uint32_t triple = (sextet_a << 18) + (sextet_b << 12) + (sextet_c << 6) + sextet_d;
|
||||
|
||||
if (j < input_length) output[j++] = (triple >> 16) & 0xFF;
|
||||
if (j < input_length) output[j++] = (triple >> 8) & 0xFF;
|
||||
if (j < input_length) output[j++] = triple & 0xFF;
|
||||
}
|
||||
|
||||
output_length = j;
|
||||
|
||||
// 移除padding
|
||||
if (input[input_length - 1] == '=') output_length--;
|
||||
if (input[input_length - 2] == '=') output_length--;
|
||||
|
||||
return output_length;
|
||||
}
|
||||
@@ -0,0 +1,34 @@
|
||||
#ifndef _BASE64_H_
|
||||
#define _BASE64_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
|
||||
/**
|
||||
* @brief Base64编码
|
||||
* @param input 输入数据
|
||||
* @param input_length 输入数据长度
|
||||
* @param output 输出缓冲区（需要预分配足够空间）
|
||||
* @return 编码后的字符串长度
|
||||
*
|
||||
* 注意：output缓冲区大小至少需要 ((input_length + 2) / 3) * 4 + 1 字节
|
||||
*/
|
||||
uint32_t base64_encode(const uint8_t* input, uint32_t input_length, char* output);
|
||||
|
||||
/**
|
||||
* @brief Base64解码
|
||||
* @param input 输入Base64字符串
|
||||
* @param input_length 输入字符串长度
|
||||
* @param output 输出缓冲区
|
||||
* @return 解码后的数据长度
|
||||
*/
|
||||
uint32_t base64_decode(const char* input, uint32_t input_length, uint8_t* output);
|
||||
|
||||
/**
|
||||
* @brief 计算Base64编码后的长度
|
||||
* @param input_length 输入数据长度
|
||||
* @return 编码后的长度（不含结束符）
|
||||
*/
|
||||
#define BASE64_ENCODE_SIZE(len) (((len) + 2) / 3 * 4)
|
||||
|
||||
#endif // _BASE64_H_
|
||||
@@ -0,0 +1,624 @@
|
||||
/*
|
||||
* ESP8266 WiFi模块驱动（支持HTTP加密传输）
|
||||
* 版本：v2.0 - 加密方案C
|
||||
* 修改：
|
||||
* 1. 添加HTTP POST请求支持
|
||||
* 2. 添加加密数据传输
|
||||
* 3. 保留原有TCP兼容接口
|
||||
*/
|
||||
|
||||
#include "esp8266.h"
|
||||
#include "Serial.h"
|
||||
#include "Delay.h"
|
||||
#include "Debug.h"
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <stdlib.h> // ← 添加atoi函数声明
|
||||
|
||||
// 外部配置（在main.c中定义）
|
||||
extern const char* WIFI_SSID;
|
||||
extern const char* WIFI_PASSWORD;
|
||||
extern const char* HTTP_SERVER_IP;
|
||||
extern const char* HTTP_SERVER_PORT;
|
||||
extern const char* HTTP_API_TOKEN;
|
||||
extern uint8_t g_server_connected;
|
||||
|
||||
/* --- 私有辅助函数 --- */
|
||||
static void ESP8266_SendCmd(const char* cmd) {
|
||||
Serial_SendString(cmd);
|
||||
Serial_SendString("\r\n");
|
||||
}
|
||||
|
||||
static uint8_t ESP8266_WaitForAck(const char* ack, uint32_t timeout) {
|
||||
uint32_t time_start = Get_Time_ms();
|
||||
uint32_t time_elapsed;
|
||||
Serial_ClearRxBuffer();
|
||||
|
||||
DEBUG_PRINT("[ESP8266] Waiting for: %s (timeout: %dms)\r\n", ack, timeout);
|
||||
|
||||
while(1) {
|
||||
time_elapsed = Get_Time_ms() - time_start;
|
||||
if (time_elapsed > timeout) {
|
||||
DEBUG_PRINT("[ESP8266] Timeout after %dms\r\n", time_elapsed);
|
||||
break;
|
||||
}
|
||||
|
||||
char* response = Serial_GetRxBuffer();
|
||||
if (response && strstr(response, ack) != NULL) {
|
||||
DEBUG_OK("[ESP8266] Received expected response");
|
||||
return ESP8266_SUCCESS;
|
||||
}
|
||||
|
||||
Delay_ms(10);
|
||||
}
|
||||
|
||||
DEBUG_PRINT("[ESP8266] Failed! Response: %s\r\n", Serial_GetRxBuffer());
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
|
||||
static uint8_t IsLeapYear(uint16_t year)
|
||||
{
|
||||
return ((year % 4 == 0 && year % 100 != 0) || (year % 400 == 0)) ? 1 : 0;
|
||||
}
|
||||
|
||||
static uint8_t DaysInMonth(uint16_t year, uint8_t month)
|
||||
{
|
||||
static const uint8_t days_table[12] = {31,28,31,30,31,30,31,31,30,31,30,31};
|
||||
if (month == 2 && IsLeapYear(year)) return 29;
|
||||
return days_table[month - 1];
|
||||
}
|
||||
|
||||
static void EpochToDateTimeUTC8(uint32_t epoch_seconds, ESP8266_DateTime* datetime)
|
||||
{
|
||||
// 转为北京时间（UTC+8）
|
||||
uint32_t total = epoch_seconds + 8U * 3600U;
|
||||
uint32_t days = total / 86400U;
|
||||
uint32_t sec_of_day = total % 86400U;
|
||||
|
||||
datetime->hour = sec_of_day / 3600U;
|
||||
datetime->minute = (sec_of_day % 3600U) / 60U;
|
||||
datetime->second = sec_of_day % 60U;
|
||||
|
||||
datetime->year = 1970;
|
||||
while (1) {
|
||||
uint16_t ydays = IsLeapYear(datetime->year) ? 366 : 365;
|
||||
if (days < ydays) break;
|
||||
days -= ydays;
|
||||
datetime->year++;
|
||||
}
|
||||
|
||||
datetime->month = 1;
|
||||
while (1) {
|
||||
uint8_t mdays = DaysInMonth(datetime->year, datetime->month);
|
||||
if (days < mdays) break;
|
||||
days -= mdays;
|
||||
datetime->month++;
|
||||
}
|
||||
|
||||
datetime->day = (uint8_t)(days + 1U);
|
||||
}
|
||||
|
||||
/* --- 公共接口函数实现 --- */
|
||||
|
||||
uint8_t ESP8266_Setup(void)
|
||||
{
|
||||
ESP8266_SendCmd("+++");
|
||||
Delay_ms(500);
|
||||
|
||||
ESP8266_SendCmd("AT");
|
||||
if (!ESP8266_WaitForAck("OK", 1000)) return ESP8266_FAIL;
|
||||
|
||||
ESP8266_SendCmd("AT+CWMODE=1");
|
||||
if (!ESP8266_WaitForAck("OK", 2000)) return ESP8266_FAIL;
|
||||
|
||||
// 先关闭可能存在的连接（避免 "link is builded" 错误）
|
||||
ESP8266_SendCmd("AT+CIPCLOSE");
|
||||
Delay_ms(500); // 等待连接关闭
|
||||
|
||||
// 设置单连接模式
|
||||
ESP8266_SendCmd("AT+CIPMUX=0");
|
||||
ESP8266_WaitForAck("OK", 1000);
|
||||
|
||||
return ESP8266_SUCCESS;
|
||||
}
|
||||
|
||||
uint8_t ESP8266_ConnectWiFi(const char* ssid, const char* password)
|
||||
{
|
||||
char cmd_buffer[128];
|
||||
|
||||
sprintf(cmd_buffer, "AT+CWJAP=\"%s\",\"%s\"", ssid, password);
|
||||
ESP8266_SendCmd(cmd_buffer);
|
||||
|
||||
return ESP8266_WaitForAck("WIFI GOT IP", 15000);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 连接到HTTP服务器（新增）
|
||||
*/
|
||||
uint8_t ESP8266_ConnectHTTPServer(const char* ip, const char* port)
|
||||
{
|
||||
char cmd_buffer[100];
|
||||
uint32_t start_time;
|
||||
|
||||
DEBUG_PRINT("[ESP8266] Connecting to HTTP server %s:%s\r\n", ip, port);
|
||||
|
||||
// 先断开之前的连接
|
||||
ESP8266_SendCmd("AT+CIPCLOSE");
|
||||
Delay_ms(500);
|
||||
|
||||
// 建立TCP连接
|
||||
sprintf(cmd_buffer, "AT+CIPSTART=\"TCP\",\"%s\",%s", ip, port);
|
||||
Serial_ClearRxBuffer();
|
||||
ESP8266_SendCmd(cmd_buffer);
|
||||
|
||||
// 等待连接成功
|
||||
start_time = Get_Time_ms();
|
||||
|
||||
while(Get_Time_ms() - start_time < 10000) {
|
||||
char* response = Serial_GetRxBuffer();
|
||||
|
||||
if (strstr(response, "CONNECT") != NULL || strstr(response, "ALREADY") != NULL) {
|
||||
DEBUG_OK("[ESP8266] HTTP server connected");
|
||||
Delay_ms(500);
|
||||
return ESP8266_SUCCESS;
|
||||
}
|
||||
|
||||
if (strstr(response, "ERROR") != NULL || strstr(response, "CLOSED") != NULL) {
|
||||
DEBUG_ERROR("[ESP8266] Connection failed");
|
||||
break;
|
||||
}
|
||||
|
||||
Delay_ms(100);
|
||||
}
|
||||
|
||||
DEBUG_ERROR("[ESP8266] Connection timeout");
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 发送加密数据（HTTP POST请求）
|
||||
*/
|
||||
uint8_t ESP8266_SendEncryptedData(const char* encrypted_data)
|
||||
{
|
||||
char http_request[1024];
|
||||
char cmd_buffer[32];
|
||||
uint32_t content_length = strlen(encrypted_data);
|
||||
|
||||
if (ESP8266_CheckConnection() != ESP8266_SUCCESS) {
|
||||
DEBUG_INFO("[ESP8266] HTTP connection not ready, reconnecting...");
|
||||
if (ESP8266_ConnectHTTPServer(HTTP_SERVER_IP, HTTP_SERVER_PORT) != ESP8266_SUCCESS) {
|
||||
DEBUG_ERROR("[ESP8266] Reconnect failed before POST");
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
g_server_connected = 1;
|
||||
}
|
||||
|
||||
// 构建HTTP POST请求
|
||||
sprintf(http_request,
|
||||
"POST /api/v1/attendance/checkins HTTP/1.1\r\n"
|
||||
"Host: %s:%s\r\n"
|
||||
"Content-Type: application/octet-stream\r\n"
|
||||
"X-Api-Token: %s\r\n"
|
||||
"X-Encrypted: AES128-CBC\r\n"
|
||||
"Content-Length: %u\r\n"
|
||||
"Connection: close\r\n"
|
||||
"\r\n"
|
||||
"%s",
|
||||
HTTP_SERVER_IP,
|
||||
HTTP_SERVER_PORT,
|
||||
HTTP_API_TOKEN,
|
||||
content_length,
|
||||
encrypted_data
|
||||
);
|
||||
|
||||
uint32_t request_len = strlen(http_request);
|
||||
|
||||
DEBUG_PRINT("[ESP8266] Sending HTTP POST (%u bytes)\r\n", request_len);
|
||||
|
||||
// 发送数据长度命令
|
||||
sprintf(cmd_buffer, "AT+CIPSEND=%u", request_len);
|
||||
Serial_ClearRxBuffer();
|
||||
ESP8266_SendCmd(cmd_buffer);
|
||||
|
||||
// 等待 ">" 提示符
|
||||
uint32_t start_time = Get_Time_ms();
|
||||
|
||||
while(Get_Time_ms() - start_time < 2000) {
|
||||
if (strstr(Serial_GetRxBuffer(), ">") != NULL) {
|
||||
DEBUG_INFO("[ESP8266] Ready to send");
|
||||
|
||||
// 发送HTTP请求
|
||||
Serial_SendString(http_request);
|
||||
Delay_ms(100);
|
||||
|
||||
// 不等待SEND OK，直接返回成功
|
||||
DEBUG_OK("[ESP8266] Data sent");
|
||||
return ESP8266_SUCCESS;
|
||||
}
|
||||
Delay_ms(10);
|
||||
}
|
||||
|
||||
DEBUG_ERROR("[ESP8266] No '>' prompt");
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
|
||||
uint8_t ESP8266_GetNetworkTime(ESP8266_DateTime* datetime)
|
||||
{
|
||||
char response_buffer[256];
|
||||
char* epoch_ptr;
|
||||
uint32_t epoch_seconds = 0;
|
||||
uint8_t digit_count = 0;
|
||||
|
||||
DEBUG_INFO("[ESP8266] Getting network time...");
|
||||
|
||||
// 优先直接请求业务服务器时间接口
|
||||
// 期望响应: {"epoch":1700000000,"server_time":"2026-02-12 12:34:56"}
|
||||
if (ESP8266_HttpGet("/api/v1/system/time", response_buffer, sizeof(response_buffer)) != ESP8266_SUCCESS) {
|
||||
DEBUG_ERROR("[ESP8266] /api/v1/system/time request failed, try reconnect...");
|
||||
if (ESP8266_ConnectHTTPServer(HTTP_SERVER_IP, HTTP_SERVER_PORT) != ESP8266_SUCCESS) {
|
||||
DEBUG_ERROR("[ESP8266] Reconnect failed when getting time");
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
g_server_connected = 1;
|
||||
if (ESP8266_HttpGet("/api/v1/system/time", response_buffer, sizeof(response_buffer)) != ESP8266_SUCCESS) {
|
||||
DEBUG_ERROR("[ESP8266] /api/v1/system/time request failed after reconnect");
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
}
|
||||
|
||||
epoch_ptr = strstr(response_buffer, "\"epoch\":");
|
||||
if (epoch_ptr == NULL) {
|
||||
DEBUG_ERROR("[ESP8266] /api/v1/system/time response missing epoch");
|
||||
DEBUG_PRINT("[ESP8266] Response: %s\r\n", response_buffer);
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
|
||||
epoch_ptr += 8; // 跳过 "epoch":
|
||||
while (*epoch_ptr == ' ' || *epoch_ptr == '\"') epoch_ptr++;
|
||||
while (*epoch_ptr >= '0' && *epoch_ptr <= '9' && digit_count < 10) {
|
||||
epoch_seconds = epoch_seconds * 10U + (uint32_t)(*epoch_ptr - '0');
|
||||
epoch_ptr++;
|
||||
digit_count++;
|
||||
}
|
||||
if (digit_count < 9) {
|
||||
DEBUG_ERROR("[ESP8266] Invalid epoch value in /api/v1/system/time response");
|
||||
DEBUG_PRINT("[ESP8266] Response: %s\r\n", response_buffer);
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
|
||||
EpochToDateTimeUTC8(epoch_seconds, datetime);
|
||||
DEBUG_PRINT("[ESP8266] Time(from server): %04d-%02d-%02d %02d:%02d:%02d\r\n",
|
||||
datetime->year, datetime->month, datetime->day,
|
||||
datetime->hour, datetime->minute, datetime->second);
|
||||
|
||||
return ESP8266_SUCCESS;
|
||||
}
|
||||
|
||||
uint8_t ESP8266_CheckConnection(void)
|
||||
{
|
||||
char* response;
|
||||
|
||||
Serial_ClearRxBuffer();
|
||||
ESP8266_SendCmd("AT+CIPSTATUS");
|
||||
Delay_ms(500);
|
||||
|
||||
response = Serial_GetRxBuffer();
|
||||
|
||||
if (strstr(response, "STATUS:3") != NULL) {
|
||||
DEBUG_INFO("[ESP8266] Connection OK (STATUS:3)");
|
||||
return ESP8266_SUCCESS;
|
||||
}
|
||||
|
||||
if (strstr(response, "STATUS:4") != NULL) {
|
||||
DEBUG_ERROR("[ESP8266] Connection closed (STATUS:4)");
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
|
||||
if (strstr(response, "STATUS:5") != NULL) {
|
||||
DEBUG_ERROR("[ESP8266] WiFi disconnected (STATUS:5)");
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
|
||||
if (strstr(response, "STATUS:2") != NULL) {
|
||||
DEBUG_ERROR("[ESP8266] Not connected to server (STATUS:2)");
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
|
||||
DEBUG_ERROR("[ESP8266] Unknown connection status");
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 发送HTTP GET请求并接收响应
|
||||
*/
|
||||
uint8_t ESP8266_HttpGet(const char* path, char* response_buffer, uint16_t buffer_size)
|
||||
{
|
||||
char http_request[256];
|
||||
char cmd_buffer[32];
|
||||
uint8_t request_sent = 0;
|
||||
|
||||
DEBUG_PRINT("[ESP8266] HTTP GET: %s\r\n", path);
|
||||
|
||||
if (response_buffer != NULL && buffer_size > 0) {
|
||||
response_buffer[0] = '\0';
|
||||
}
|
||||
|
||||
if (ESP8266_CheckConnection() != ESP8266_SUCCESS) {
|
||||
DEBUG_INFO("[ESP8266] HTTP connection not ready, reconnecting...");
|
||||
if (ESP8266_ConnectHTTPServer(HTTP_SERVER_IP, HTTP_SERVER_PORT) != ESP8266_SUCCESS) {
|
||||
DEBUG_ERROR("[ESP8266] Reconnect failed before GET");
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
g_server_connected = 1;
|
||||
}
|
||||
|
||||
// 构建HTTP GET请求
|
||||
sprintf(http_request,
|
||||
"GET %s HTTP/1.1\r\n"
|
||||
"Host: %s:%s\r\n"
|
||||
"X-Api-Token: %s\r\n"
|
||||
"Connection: close\r\n"
|
||||
"\r\n",
|
||||
path,
|
||||
HTTP_SERVER_IP,
|
||||
HTTP_SERVER_PORT,
|
||||
HTTP_API_TOKEN
|
||||
);
|
||||
|
||||
uint32_t request_len = strlen(http_request);
|
||||
|
||||
// 发送数据长度命令
|
||||
sprintf(cmd_buffer, "AT+CIPSEND=%u", request_len);
|
||||
Serial_ClearRxBuffer();
|
||||
ESP8266_SendCmd(cmd_buffer);
|
||||
|
||||
// 等待 ">" 提示符
|
||||
uint32_t start_time = Get_Time_ms();
|
||||
|
||||
while(Get_Time_ms() - start_time < 2000) {
|
||||
if (strstr(Serial_GetRxBuffer(), ">") != NULL) {
|
||||
DEBUG_INFO("[ESP8266] Ready to send GET request");
|
||||
|
||||
// 发送HTTP GET请求
|
||||
Serial_SendString(http_request);
|
||||
request_sent = 1;
|
||||
break;
|
||||
}
|
||||
Delay_ms(10);
|
||||
}
|
||||
|
||||
if (!request_sent) {
|
||||
DEBUG_ERROR("[ESP8266] No '>' prompt for GET request");
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
|
||||
// 等待接收完整响应（最多8秒）
|
||||
start_time = Get_Time_ms();
|
||||
uint8_t found_header = 0;
|
||||
uint32_t content_length = 0;
|
||||
|
||||
while(Get_Time_ms() - start_time < 8000) {
|
||||
char* response = Serial_GetRxBuffer();
|
||||
|
||||
// 1. 处理+IPD前缀（ESP8266格式：+IPD,长度:数据）
|
||||
char* ipd_marker = strstr(response, "+IPD,");
|
||||
if (ipd_marker != NULL) {
|
||||
// 跳过 "+IPD," 找到实际数据
|
||||
char* data_start = strchr(ipd_marker, ':');
|
||||
if (data_start != NULL) {
|
||||
data_start++; // 跳过 ':'
|
||||
response = data_start; // 从这里开始才是HTTP响应
|
||||
}
|
||||
}
|
||||
|
||||
// 2. 查找HTTP响应体（JSON数据在\r\n\r\n之后）
|
||||
char* body_start = strstr(response, "\r\n\r\n");
|
||||
if (body_start != NULL) {
|
||||
body_start += 4; // 跳过 \r\n\r\n
|
||||
|
||||
// 3. 如果还没提取Content-Length，尝试提取
|
||||
if (!found_header) {
|
||||
char* cl_str = strstr(response, "Content-Length:");
|
||||
if (cl_str != NULL) {
|
||||
cl_str += 15; // 跳过 "Content-Length:"
|
||||
while (*cl_str == ' ') cl_str++;
|
||||
content_length = atoi(cl_str);
|
||||
DEBUG_PRINT("[ESP8266] Content-Length: %u\r\n", content_length);
|
||||
found_header = 1;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. 检查是否接收完整（比较实际长度和Content-Length）
|
||||
uint16_t body_len = strlen(body_start);
|
||||
|
||||
// 移除末尾的 "CLOSED" "OK" 等ESP8266附加信息
|
||||
char* closed_marker = strstr(body_start, "\r\nCLOSED");
|
||||
if (closed_marker != NULL) {
|
||||
*closed_marker = '\0';
|
||||
body_len = strlen(body_start);
|
||||
}
|
||||
// 同时处理没有\r\n的情况
|
||||
closed_marker = strstr(body_start, "CLOSED");
|
||||
if (closed_marker != NULL) {
|
||||
*closed_marker = '\0';
|
||||
body_len = strlen(body_start);
|
||||
}
|
||||
// 移除末尾的OK
|
||||
char* ok_marker = strstr(body_start, "\r\nOK");
|
||||
if (ok_marker != NULL) {
|
||||
*ok_marker = '\0';
|
||||
body_len = strlen(body_start);
|
||||
}
|
||||
|
||||
// 5. 如果数据完整或超时，复制到缓冲区
|
||||
if ((found_header && body_len >= content_length) ||
|
||||
(Get_Time_ms() - start_time > 3000 && body_len > 0)) {
|
||||
if (body_len >= buffer_size) {
|
||||
body_len = buffer_size - 1;
|
||||
}
|
||||
|
||||
strncpy(response_buffer, body_start, body_len);
|
||||
response_buffer[body_len] = '\0';
|
||||
|
||||
DEBUG_PRINT("[ESP8266] Received response (%d bytes)\r\n", strlen(response_buffer));
|
||||
DEBUG_PRINT("[ESP8266] Response: %s\r\n", response_buffer);
|
||||
return ESP8266_SUCCESS;
|
||||
}
|
||||
}
|
||||
|
||||
Delay_ms(100);
|
||||
}
|
||||
|
||||
DEBUG_ERROR("[ESP8266] No valid HTTP response or timeout");
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
|
||||
// ========== 兼容旧版本的函数 ==========
|
||||
|
||||
/**
|
||||
* @brief 查询学生在指定时段是否已签到（服务器端查重）
|
||||
* @param student_id 学号
|
||||
* @param slot_start 时段开始时间（格式"HH:MM"）
|
||||
* @param slot_end 时段结束时间（格式"HH:MM"）
|
||||
* @retval 1 表示已签到（重复）, 0 表示未签到
|
||||
*/
|
||||
uint8_t ESP8266_CheckDuplicate(const char* student_id, const char* slot_start, const char* slot_end)
|
||||
{
|
||||
char path[128];
|
||||
char response_buffer[256];
|
||||
|
||||
// 构建查询路径
|
||||
sprintf(path, "/api/v1/attendance/duplicates?student_id=%s&slot_start=%s&slot_end=%s",
|
||||
student_id, slot_start, slot_end);
|
||||
|
||||
DEBUG_PRINT("[ESP8266] Checking duplicate: %s\r\n", path);
|
||||
|
||||
// 先检查连接状态，如果断开则重连
|
||||
if (ESP8266_CheckConnection() != ESP8266_SUCCESS) {
|
||||
DEBUG_INFO("[ESP8266] Connection lost, reconnecting...");
|
||||
extern const char* HTTP_SERVER_IP;
|
||||
extern const char* HTTP_SERVER_PORT;
|
||||
if (ESP8266_ConnectHTTPServer(HTTP_SERVER_IP, HTTP_SERVER_PORT) != ESP8266_SUCCESS) {
|
||||
DEBUG_ERROR("[ESP8266] Reconnect failed");
|
||||
return 0; // 连接失败，默认允许签到
|
||||
}
|
||||
Delay_ms(200); // 等待连接稳定
|
||||
}
|
||||
|
||||
// 发送HTTP GET请求
|
||||
if (ESP8266_HttpGet(path, response_buffer, sizeof(response_buffer)) == ESP8266_SUCCESS) {
|
||||
// 解析响应，查找 "duplicate":true
|
||||
if (strstr(response_buffer, "\"duplicate\":true") != NULL) {
|
||||
DEBUG_INFO("[ESP8266] Duplicate found on server!");
|
||||
return 1; // 已签到
|
||||
} else {
|
||||
DEBUG_INFO("[ESP8266] No duplicate found");
|
||||
return 0; // 未签到
|
||||
}
|
||||
}
|
||||
|
||||
DEBUG_ERROR("[ESP8266] Failed to check duplicate, assuming not duplicate");
|
||||
return 0; // 查询失败时默认为未签到，允许本地签到
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 下载今日已签到学生列表（开机时调用）
|
||||
* @param slot_start 时段开始时间（格式"HH:MM"）
|
||||
* @param slot_end 时段结束时间（格式"HH:MM"）
|
||||
* @param student_ids 输出：学号数组（逗号分隔的字符串）
|
||||
* @param buffer_size 缓冲区大小
|
||||
* @retval 成功下载的学号数量
|
||||
*/
|
||||
uint8_t ESP8266_DownloadTodayRecords(const char* slot_start, const char* slot_end, char* student_ids, uint16_t buffer_size)
|
||||
{
|
||||
char path[128];
|
||||
char response_buffer[512];
|
||||
|
||||
// 构建查询路径
|
||||
sprintf(path, "/api/v1/attendance/today?slot_start=%s&slot_end=%s", slot_start, slot_end);
|
||||
|
||||
DEBUG_PRINT("[ESP8266] Downloading today's records: %s\r\n", path);
|
||||
|
||||
// 先检查连接状态，如果断开则重连
|
||||
if (ESP8266_CheckConnection() != ESP8266_SUCCESS) {
|
||||
DEBUG_INFO("[ESP8266] Connection lost, reconnecting before download...");
|
||||
extern const char* HTTP_SERVER_IP;
|
||||
extern const char* HTTP_SERVER_PORT;
|
||||
if (ESP8266_ConnectHTTPServer(HTTP_SERVER_IP, HTTP_SERVER_PORT) != ESP8266_SUCCESS) {
|
||||
DEBUG_ERROR("[ESP8266] Reconnect failed");
|
||||
return 0;
|
||||
}
|
||||
Delay_ms(300); // 等待连接稳定
|
||||
}
|
||||
|
||||
// 发送HTTP GET请求
|
||||
if (ESP8266_HttpGet(path, response_buffer, sizeof(response_buffer)) != ESP8266_SUCCESS) {
|
||||
DEBUG_ERROR("[ESP8266] Failed to download today's records");
|
||||
return 0;
|
||||
}
|
||||
|
||||
// 解析响应，提取学号列表
|
||||
// 格式: {"date":"2026-02-07","records":["1","2","3"]}
|
||||
char* records_start = strstr(response_buffer, "\"records\":[");
|
||||
if (records_start == NULL) {
|
||||
DEBUG_ERROR("[ESP8266] Invalid response format");
|
||||
return 0;
|
||||
}
|
||||
|
||||
records_start += 11; // 跳过 "records":[
|
||||
char* records_end = strchr(records_start, ']');
|
||||
if (records_end == NULL) {
|
||||
DEBUG_ERROR("[ESP8266] Invalid response format");
|
||||
return 0;
|
||||
}
|
||||
|
||||
// 复制学号列表到输出缓冲区
|
||||
uint16_t len = records_end - records_start;
|
||||
if (len >= buffer_size) len = buffer_size - 1;
|
||||
|
||||
strncpy(student_ids, records_start, len);
|
||||
student_ids[len] = '\0';
|
||||
|
||||
// 统计学号数量（空列表返回0）
|
||||
uint8_t count = 0;
|
||||
if (len > 2) { // 至少有一个学号 "x"
|
||||
count = 1;
|
||||
for (uint16_t i = 0; i < len; i++) {
|
||||
if (student_ids[i] == ',') count++;
|
||||
}
|
||||
}
|
||||
|
||||
DEBUG_PRINT("[ESP8266] Downloaded %d records: %s\r\n", count, student_ids);
|
||||
return count;
|
||||
}
|
||||
|
||||
uint8_t ESP8266_ConnectTCPServer(const char* ip, const char* port)
|
||||
{
|
||||
// 重定向到HTTP版本
|
||||
return ESP8266_ConnectHTTPServer(ip, port);
|
||||
}
|
||||
|
||||
uint8_t ESP8266_SendData(char* Data)
|
||||
{
|
||||
char cmd_buffer[32];
|
||||
uint16_t data_len = strlen(Data);
|
||||
|
||||
DEBUG_PRINT("[ESP8266] Sending %d bytes (legacy mode)\r\n", data_len);
|
||||
|
||||
sprintf(cmd_buffer, "AT+CIPSEND=%d", data_len);
|
||||
ESP8266_SendCmd(cmd_buffer);
|
||||
|
||||
uint32_t start_time = Get_Time_ms();
|
||||
Serial_ClearRxBuffer();
|
||||
|
||||
while(Get_Time_ms() - start_time < 1000) {
|
||||
if (strstr(Serial_GetRxBuffer(), ">") != NULL) {
|
||||
Serial_SendString(Data);
|
||||
Delay_ms(50);
|
||||
return ESP8266_SUCCESS;
|
||||
}
|
||||
Delay_ms(10);
|
||||
}
|
||||
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
@@ -0,0 +1,98 @@
|
||||
#ifndef __ESP8266_H
|
||||
#define __ESP8266_H
|
||||
|
||||
#include "stm32f10x.h"
|
||||
|
||||
// 定义布尔类型，方便返回状态
|
||||
#define ESP8266_SUCCESS 1
|
||||
#define ESP8266_FAIL 0
|
||||
|
||||
// 时间结构体
|
||||
typedef struct {
|
||||
uint16_t year;
|
||||
uint8_t month;
|
||||
uint8_t day;
|
||||
uint8_t hour;
|
||||
uint8_t minute;
|
||||
uint8_t second;
|
||||
} ESP8266_DateTime;
|
||||
|
||||
/*
|
||||
--- 公共函数接口 ---
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 对ESP8266模块进行基础设置
|
||||
* @retval 1 表示成功, 0 表示失败
|
||||
*/
|
||||
uint8_t ESP8266_Setup(void);
|
||||
|
||||
/**
|
||||
* @brief 命令ESP8266连接到指定的WiFi网络
|
||||
* @param ssid 要连接的WiFi名称 (SSID)
|
||||
* @param password WiFi的密码
|
||||
* @retval 1 表示成功, 0 表示失败
|
||||
*/
|
||||
uint8_t ESP8266_ConnectWiFi(const char* ssid, const char* password);
|
||||
|
||||
/**
|
||||
* @brief 命令ESP8266连接到HTTP服务器（新增）
|
||||
* @param ip 服务器的IP地址
|
||||
* @param port 服务器的端口号
|
||||
* @retval 1 表示成功, 0 表示失败
|
||||
*/
|
||||
uint8_t ESP8266_ConnectHTTPServer(const char* ip, const char* port);
|
||||
|
||||
/**
|
||||
* @brief 通过ESP8266发送HTTP POST请求（新增 - 加密版本）
|
||||
* @param encrypted_data 加密后的Base64数据
|
||||
* @retval 1 表示成功, 0 表示失败
|
||||
*/
|
||||
uint8_t ESP8266_SendEncryptedData(const char* encrypted_data);
|
||||
|
||||
/**
|
||||
* @brief 检查TCP连接是否正常
|
||||
* @retval 1 表示已连接, 0 表示未连接
|
||||
*/
|
||||
uint8_t ESP8266_CheckConnection(void);
|
||||
|
||||
/**
|
||||
* @brief 从网络获取当前时间（NTP/SNTP）
|
||||
* @param datetime 时间结构体指针，用于存储获取的时间
|
||||
* @retval 1 表示成功, 0 表示失败
|
||||
*/
|
||||
uint8_t ESP8266_GetNetworkTime(ESP8266_DateTime* datetime);
|
||||
|
||||
/**
|
||||
* @brief 发送HTTP GET请求并接收响应（新增）
|
||||
* @param path 请求路径（如"/api/v1/config/time-slots"）
|
||||
* @param response_buffer 接收响应数据的缓冲区
|
||||
* @param buffer_size 缓冲区大小
|
||||
* @retval 1 表示成功, 0 表示失败
|
||||
*/
|
||||
uint8_t ESP8266_HttpGet(const char* path, char* response_buffer, uint16_t buffer_size);
|
||||
|
||||
/**
|
||||
* @brief 查询学生在指定时段是否已签到（服务器端查重）
|
||||
* @param student_id 学号
|
||||
* @param slot_start 时段开始时间（格式"HH:MM"）
|
||||
* @param slot_end 时段结束时间（格式"HH:MM"）
|
||||
* @retval 1 表示已签到（重复）, 0 表示未签到
|
||||
*/
|
||||
uint8_t ESP8266_CheckDuplicate(const char* student_id, const char* slot_start, const char* slot_end);
|
||||
|
||||
/**
|
||||
* @brief 下载今日已签到学生列表（开机时调用）
|
||||
* @param slot_start 时段开始时间（格式"HH:MM"）
|
||||
* @param slot_end 时段结束时间（格式"HH:MM"）
|
||||
* @param student_ids 输出：学号数组（逗号分隔的字符串）
|
||||
* @param buffer_size 缓冲区大小
|
||||
* @retval 成功下载的学号数量
|
||||
*/
|
||||
uint8_t ESP8266_DownloadTodayRecords(const char* slot_start, const char* slot_end, char* student_ids, uint16_t buffer_size);
|
||||
|
||||
// 兼容旧版本（已废弃，建议使用HTTP版本）
|
||||
uint8_t ESP8266_ConnectTCPServer(const char* ip, const char* port);
|
||||
uint8_t ESP8266_SendData(char* Data);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,243 @@
|
||||
/*
|
||||
* ESP8266 WiFi模块驱动（支持HTTP加密传输）
|
||||
* 新增功能：
|
||||
* 1. HTTP POST请求支持
|
||||
* 2. 加密数据传输
|
||||
* 3. 自动重连机制
|
||||
*/
|
||||
|
||||
#include "esp8266.h"
|
||||
#include "Serial.h"
|
||||
#include "Delay.h"
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
// 外部配置（在main.c中定义）
|
||||
extern const char* WIFI_SSID;
|
||||
extern const char* WIFI_PASSWORD;
|
||||
extern const char* HTTP_SERVER_IP;
|
||||
extern const char* HTTP_SERVER_PORT;
|
||||
extern const char* HTTP_API_TOKEN;
|
||||
|
||||
// 内部函数声明
|
||||
static uint8_t ESP8266_SendCommand(const char* cmd, const char* expected, uint16_t timeout);
|
||||
static void ESP8266_ClearBuffer(void);
|
||||
|
||||
/**
|
||||
* @brief 发送AT命令并等待响应
|
||||
*/
|
||||
static uint8_t ESP8266_SendCommand(const char* cmd, const char* expected, uint16_t timeout)
|
||||
{
|
||||
Serial_SendString(cmd);
|
||||
Serial_SendString("\r\n");
|
||||
|
||||
Delay_ms(timeout);
|
||||
|
||||
if (expected == NULL) {
|
||||
return ESP8266_SUCCESS;
|
||||
}
|
||||
|
||||
// 检查是否收到期望的响应
|
||||
char* response = Serial_GetRxData();
|
||||
if (strstr(response, expected) != NULL) {
|
||||
return ESP8266_SUCCESS;
|
||||
}
|
||||
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
|
||||
static void ESP8266_ClearBuffer(void)
|
||||
{
|
||||
Serial_ClearRxBuffer();
|
||||
}
|
||||
|
||||
uint8_t ESP8266_Setup(void)
|
||||
{
|
||||
ESP8266_ClearBuffer();
|
||||
|
||||
// 测试AT指令
|
||||
if (ESP8266_SendCommand("AT", "OK", 1000) == ESP8266_FAIL) {
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
|
||||
// 设置为STA模式（客户端模式）
|
||||
if (ESP8266_SendCommand("AT+CWMODE=1", "OK", 1000) == ESP8266_FAIL) {
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
|
||||
// 关闭回显
|
||||
ESP8266_SendCommand("ATE0", "OK", 500);
|
||||
|
||||
// 设置单连接模式
|
||||
if (ESP8266_SendCommand("AT+CIPMUX=0", "OK", 1000) == ESP8266_FAIL) {
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
|
||||
return ESP8266_SUCCESS;
|
||||
}
|
||||
|
||||
uint8_t ESP8266_ConnectWiFi(const char* ssid, const char* password)
|
||||
{
|
||||
char cmd[128];
|
||||
|
||||
ESP8266_ClearBuffer();
|
||||
|
||||
// 断开之前的WiFi连接
|
||||
ESP8266_SendCommand("AT+CWQAP", "OK", 1000);
|
||||
Delay_ms(1000);
|
||||
|
||||
// 连接到WiFi
|
||||
sprintf(cmd, "AT+CWJAP=\"%s\",\"%s\"", ssid, password);
|
||||
|
||||
// WiFi连接可能需要较长时间
|
||||
if (ESP8266_SendCommand(cmd, "OK", 10000) == ESP8266_FAIL) {
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
|
||||
Delay_ms(2000);
|
||||
return ESP8266_SUCCESS;
|
||||
}
|
||||
|
||||
uint8_t ESP8266_ConnectHTTPServer(const char* ip, const char* port)
|
||||
{
|
||||
char cmd[64];
|
||||
|
||||
ESP8266_ClearBuffer();
|
||||
|
||||
// 断开之前的TCP连接
|
||||
ESP8266_SendCommand("AT+CIPCLOSE", "OK", 1000);
|
||||
Delay_ms(500);
|
||||
|
||||
// 建立TCP连接到HTTP服务器
|
||||
sprintf(cmd, "AT+CIPSTART=\"TCP\",\"%s\",%s", ip, port);
|
||||
|
||||
if (ESP8266_SendCommand(cmd, "OK", 5000) == ESP8266_FAIL) {
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
|
||||
Delay_ms(1000);
|
||||
return ESP8266_SUCCESS;
|
||||
}
|
||||
|
||||
uint8_t ESP8266_SendEncryptedData(const char* encrypted_data)
|
||||
{
|
||||
char http_request[1024];
|
||||
char cmd[32];
|
||||
uint32_t content_length = strlen(encrypted_data);
|
||||
|
||||
// 构建HTTP POST请求
|
||||
sprintf(http_request,
|
||||
"POST /api/v1/attendance/checkins HTTP/1.1\r\n"
|
||||
"Host: %s:%s\r\n"
|
||||
"Content-Type: application/octet-stream\r\n"
|
||||
"X-Api-Token: %s\r\n"
|
||||
"X-Encrypted: AES128-CBC\r\n"
|
||||
"Content-Length: %u\r\n"
|
||||
"Connection: keep-alive\r\n"
|
||||
"\r\n"
|
||||
"%s",
|
||||
HTTP_SERVER_IP,
|
||||
HTTP_SERVER_PORT,
|
||||
HTTP_API_TOKEN,
|
||||
content_length,
|
||||
encrypted_data
|
||||
);
|
||||
|
||||
uint32_t request_len = strlen(http_request);
|
||||
|
||||
// 发送数据长度命令
|
||||
sprintf(cmd, "AT+CIPSEND=%u", request_len);
|
||||
|
||||
ESP8266_ClearBuffer();
|
||||
|
||||
if (ESP8266_SendCommand(cmd, ">", 2000) == ESP8266_FAIL) {
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
|
||||
// 发送HTTP请求
|
||||
Serial_SendString(http_request);
|
||||
|
||||
// 等待发送完成（不阻塞太久）
|
||||
Delay_ms(100);
|
||||
|
||||
// 可选：等待服务器响应（检查是否有"200 OK"）
|
||||
// 但为了不阻塞，建议不等待
|
||||
|
||||
return ESP8266_SUCCESS;
|
||||
}
|
||||
|
||||
uint8_t ESP8266_CheckConnection(void)
|
||||
{
|
||||
ESP8266_ClearBuffer();
|
||||
|
||||
if (ESP8266_SendCommand("AT+CIPSTATUS", "OK", 1000) == ESP8266_FAIL) {
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
|
||||
// 检查响应中是否包含"STATUS:3"（已连接）
|
||||
char* response = Serial_GetRxData();
|
||||
if (strstr(response, "STATUS:3") != NULL ||
|
||||
strstr(response, "STATUS:4") != NULL) {
|
||||
return ESP8266_SUCCESS;
|
||||
}
|
||||
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
|
||||
uint8_t ESP8266_GetNetworkTime(ESP8266_DateTime* datetime)
|
||||
{
|
||||
// 启用SNTP
|
||||
if (ESP8266_SendCommand("AT+CIPSNTPCFG=1,8,\"pool.ntp.org\"", "OK", 2000) == ESP8266_FAIL) {
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
|
||||
Delay_ms(3000); // 等待时间同步
|
||||
|
||||
ESP8266_ClearBuffer();
|
||||
|
||||
// 获取时间
|
||||
if (ESP8266_SendCommand("AT+CIPSNTPTIME?", "OK", 1000) == ESP8266_FAIL) {
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
|
||||
// 解析响应（格式：+CIPSNTPTIME:Thu Jan 01 08:00:00 2024）
|
||||
char* response = Serial_GetRxData();
|
||||
char* time_str = strstr(response, "+CIPSNTPTIME:");
|
||||
|
||||
if (time_str != NULL) {
|
||||
// 简单解析（这里只是示例，实际需要更完善的解析）
|
||||
sscanf(time_str, "+CIPSNTPTIME:%*s %*s %d %d:%d:%d %d",
|
||||
&datetime->day, &datetime->hour,
|
||||
&datetime->minute, &datetime->second, &datetime->year);
|
||||
|
||||
return ESP8266_SUCCESS;
|
||||
}
|
||||
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
|
||||
// ========== 兼容旧版本的函数（已废弃） ==========
|
||||
|
||||
uint8_t ESP8266_ConnectTCPServer(const char* ip, const char* port)
|
||||
{
|
||||
// 重定向到HTTP版本
|
||||
return ESP8266_ConnectHTTPServer(ip, port);
|
||||
}
|
||||
|
||||
uint8_t ESP8266_SendData(char* Data)
|
||||
{
|
||||
// 警告：此函数已废弃，请使用ESP8266_SendEncryptedData
|
||||
// 为了兼容，这里保留基本实现
|
||||
char cmd[32];
|
||||
|
||||
sprintf(cmd, "AT+CIPSEND=%d", strlen(Data));
|
||||
|
||||
if (ESP8266_SendCommand(cmd, ">", 2000) == ESP8266_FAIL) {
|
||||
return ESP8266_FAIL;
|
||||
}
|
||||
|
||||
Serial_SendString(Data);
|
||||
Delay_ms(50);
|
||||
|
||||
return ESP8266_SUCCESS;
|
||||
}
|
||||
@@ -0,0 +1,70 @@
|
||||
#ifndef __ESP8266_H
|
||||
#define __ESP8266_H
|
||||
|
||||
#include "stm32f10x.h"
|
||||
|
||||
// 定义布尔类型，方便返回状态
|
||||
#define ESP8266_SUCCESS 1
|
||||
#define ESP8266_FAIL 0
|
||||
|
||||
// 时间结构体
|
||||
typedef struct {
|
||||
uint16_t year;
|
||||
uint8_t month;
|
||||
uint8_t day;
|
||||
uint8_t hour;
|
||||
uint8_t minute;
|
||||
uint8_t second;
|
||||
} ESP8266_DateTime;
|
||||
|
||||
/*
|
||||
--- 公共函数接口 ---
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief 对ESP8266模块进行基础设置
|
||||
* @retval 1 表示成功, 0 表示失败
|
||||
*/
|
||||
uint8_t ESP8266_Setup(void);
|
||||
|
||||
/**
|
||||
* @brief 命令ESP8266连接到指定的WiFi网络
|
||||
* @param ssid 要连接的WiFi名称 (SSID)
|
||||
* @param password WiFi的密码
|
||||
* @retval 1 表示成功, 0 表示失败
|
||||
*/
|
||||
uint8_t ESP8266_ConnectWiFi(const char* ssid, const char* password);
|
||||
|
||||
/**
|
||||
* @brief 命令ESP8266连接到HTTP服务器（新增）
|
||||
* @param ip 服务器的IP地址
|
||||
* @param port 服务器的端口号
|
||||
* @retval 1 表示成功, 0 表示失败
|
||||
*/
|
||||
uint8_t ESP8266_ConnectHTTPServer(const char* ip, const char* port);
|
||||
|
||||
/**
|
||||
* @brief 通过ESP8266发送HTTP POST请求（新增 - 加密版本）
|
||||
* @param encrypted_data 加密后的Base64数据
|
||||
* @retval 1 表示成功, 0 表示失败
|
||||
*/
|
||||
uint8_t ESP8266_SendEncryptedData(const char* encrypted_data);
|
||||
|
||||
/**
|
||||
* @brief 检查TCP连接是否正常
|
||||
* @retval 1 表示已连接, 0 表示未连接
|
||||
*/
|
||||
uint8_t ESP8266_CheckConnection(void);
|
||||
|
||||
/**
|
||||
* @brief 从网络获取当前时间（NTP/SNTP）
|
||||
* @param datetime 时间结构体指针，用于存储获取的时间
|
||||
* @retval 1 表示成功, 0 表示失败
|
||||
*/
|
||||
uint8_t ESP8266_GetNetworkTime(ESP8266_DateTime* datetime);
|
||||
|
||||
// 兼容旧版本（已废弃，建议使用HTTP版本）
|
||||
uint8_t ESP8266_ConnectTCPServer(const char* ip, const char* port);
|
||||
uint8_t ESP8266_SendData(char* Data);
|
||||
|
||||
#endif
|
||||
+225
@@ -0,0 +1,225 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file misc.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the miscellaneous firmware functions (add-on
|
||||
* to CMSIS functions).
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "misc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC
|
||||
* @brief MISC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the priority grouping: pre-emption priority and subpriority.
|
||||
* @param NVIC_PriorityGroup: specifies the priority grouping bits length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
|
||||
* 4 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
|
||||
* 3 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
|
||||
* 2 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
|
||||
* 1 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
|
||||
* 0 bits for subpriority
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
|
||||
|
||||
/* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
|
||||
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the NVIC peripheral according to the specified
|
||||
* parameters in the NVIC_InitStruct.
|
||||
* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
|
||||
* the configuration information for the specified NVIC peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
|
||||
{
|
||||
uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
|
||||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
|
||||
assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
|
||||
|
||||
if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
|
||||
{
|
||||
/* Compute the Corresponding IRQ Priority --------------------------------*/
|
||||
tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
|
||||
tmppre = (0x4 - tmppriority);
|
||||
tmpsub = tmpsub >> tmppriority;
|
||||
|
||||
tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
|
||||
tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
|
||||
tmppriority = tmppriority << 0x04;
|
||||
|
||||
NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
|
||||
|
||||
/* Enable the Selected IRQ Channels --------------------------------------*/
|
||||
NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
|
||||
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the Selected IRQ Channels -------------------------------------*/
|
||||
NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
|
||||
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the vector table location and Offset.
|
||||
* @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_VectTab_RAM
|
||||
* @arg NVIC_VectTab_FLASH
|
||||
* @param Offset: Vector Table base offset field. This value must be a multiple
|
||||
* of 0x200.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
|
||||
assert_param(IS_NVIC_OFFSET(Offset));
|
||||
|
||||
SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the condition for the system to enter low power mode.
|
||||
* @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_LP_SEVONPEND
|
||||
* @arg NVIC_LP_SLEEPDEEP
|
||||
* @arg NVIC_LP_SLEEPONEXIT
|
||||
* @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_LP(LowPowerMode));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
SCB->SCR |= LowPowerMode;
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the SysTick clock source.
|
||||
* @param SysTick_CLKSource: specifies the SysTick clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
|
||||
* @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
|
||||
* @retval None
|
||||
*/
|
||||
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
|
||||
if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
|
||||
{
|
||||
SysTick->CTRL |= SysTick_CLKSource_HCLK;
|
||||
}
|
||||
else
|
||||
{
|
||||
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
+220
@@ -0,0 +1,220 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file misc.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the miscellaneous
|
||||
* firmware library functions (add-on to CMSIS functions).
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __MISC_H
|
||||
#define __MISC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief NVIC Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
|
||||
This parameter can be a value of @ref IRQn_Type
|
||||
(For the complete STM32 Devices IRQ Channels list, please
|
||||
refer to stm32f10x.h file) */
|
||||
|
||||
uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
|
||||
specified in NVIC_IRQChannel. This parameter can be a value
|
||||
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
|
||||
|
||||
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
|
||||
in NVIC_IRQChannel. This parameter can be a value
|
||||
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
|
||||
|
||||
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
|
||||
will be enabled or disabled.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
} NVIC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup NVIC_Priority_Table
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
@code
|
||||
The table below gives the allowed values of the pre-emption priority and subpriority according
|
||||
to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
|
||||
============================================================================================================================
|
||||
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
|
||||
============================================================================================================================
|
||||
NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
|
||||
| | | 4 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
|
||||
| | | 3 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
|
||||
| | | 2 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
|
||||
| | | 1 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
|
||||
| | | 0 bits for subpriority
|
||||
============================================================================================================================
|
||||
@endcode
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup Vector_Table_Base
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
|
||||
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
|
||||
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
|
||||
((VECTTAB) == NVIC_VectTab_FLASH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup System_Low_Power
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
|
||||
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
|
||||
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
|
||||
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
|
||||
((LP) == NVIC_LP_SLEEPDEEP) || \
|
||||
((LP) == NVIC_LP_SLEEPONEXIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Preemption_Priority_Group
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
|
||||
1 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
|
||||
0 bits for subpriority */
|
||||
|
||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
|
||||
((GROUP) == NVIC_PriorityGroup_1) || \
|
||||
((GROUP) == NVIC_PriorityGroup_2) || \
|
||||
((GROUP) == NVIC_PriorityGroup_3) || \
|
||||
((GROUP) == NVIC_PriorityGroup_4))
|
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||
|
||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||
|
||||
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SysTick_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
|
||||
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
|
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
|
||||
((SOURCE) == SysTick_CLKSource_HCLK_Div8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
|
||||
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
|
||||
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
|
||||
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
|
||||
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MISC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,483 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_adc.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the ADC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_ADC_H
|
||||
#define __STM32F10x_ADC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ADC Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or
|
||||
dual mode.
|
||||
This parameter can be a value of @ref ADC_mode */
|
||||
|
||||
FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in
|
||||
Scan (multichannels) or Single (one channel) mode.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
|
||||
Continuous or Single mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog
|
||||
to digital conversion of regular channels. This parameter
|
||||
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
|
||||
|
||||
uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
|
||||
This parameter can be a value of @ref ADC_data_align */
|
||||
|
||||
uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted
|
||||
using the sequencer for regular channel group.
|
||||
This parameter must range from 1 to 16. */
|
||||
}ADC_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
|
||||
((PERIPH) == ADC2) || \
|
||||
((PERIPH) == ADC3))
|
||||
|
||||
#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
|
||||
((PERIPH) == ADC3))
|
||||
|
||||
/** @defgroup ADC_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_Mode_Independent ((uint32_t)0x00000000)
|
||||
#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)
|
||||
#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)
|
||||
#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)
|
||||
#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)
|
||||
#define ADC_Mode_InjecSimult ((uint32_t)0x00050000)
|
||||
#define ADC_Mode_RegSimult ((uint32_t)0x00060000)
|
||||
#define ADC_Mode_FastInterl ((uint32_t)0x00070000)
|
||||
#define ADC_Mode_SlowInterl ((uint32_t)0x00080000)
|
||||
#define ADC_Mode_AlterTrig ((uint32_t)0x00090000)
|
||||
|
||||
#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
|
||||
((MODE) == ADC_Mode_RegInjecSimult) || \
|
||||
((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
|
||||
((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
|
||||
((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
|
||||
((MODE) == ADC_Mode_InjecSimult) || \
|
||||
((MODE) == ADC_Mode_RegSimult) || \
|
||||
((MODE) == ADC_Mode_FastInterl) || \
|
||||
((MODE) == ADC_Mode_SlowInterl) || \
|
||||
((MODE) == ADC_Mode_AlterTrig))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */
|
||||
|
||||
#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */
|
||||
#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */
|
||||
|
||||
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */
|
||||
|
||||
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_None) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_data_align
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
|
||||
#define ADC_DataAlign_Left ((uint32_t)0x00000800)
|
||||
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
|
||||
((ALIGN) == ADC_DataAlign_Left))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_channels
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_Channel_0 ((uint8_t)0x00)
|
||||
#define ADC_Channel_1 ((uint8_t)0x01)
|
||||
#define ADC_Channel_2 ((uint8_t)0x02)
|
||||
#define ADC_Channel_3 ((uint8_t)0x03)
|
||||
#define ADC_Channel_4 ((uint8_t)0x04)
|
||||
#define ADC_Channel_5 ((uint8_t)0x05)
|
||||
#define ADC_Channel_6 ((uint8_t)0x06)
|
||||
#define ADC_Channel_7 ((uint8_t)0x07)
|
||||
#define ADC_Channel_8 ((uint8_t)0x08)
|
||||
#define ADC_Channel_9 ((uint8_t)0x09)
|
||||
#define ADC_Channel_10 ((uint8_t)0x0A)
|
||||
#define ADC_Channel_11 ((uint8_t)0x0B)
|
||||
#define ADC_Channel_12 ((uint8_t)0x0C)
|
||||
#define ADC_Channel_13 ((uint8_t)0x0D)
|
||||
#define ADC_Channel_14 ((uint8_t)0x0E)
|
||||
#define ADC_Channel_15 ((uint8_t)0x0F)
|
||||
#define ADC_Channel_16 ((uint8_t)0x10)
|
||||
#define ADC_Channel_17 ((uint8_t)0x11)
|
||||
|
||||
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
|
||||
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
|
||||
|
||||
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
|
||||
((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
|
||||
((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
|
||||
((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
|
||||
((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
|
||||
((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
|
||||
((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
|
||||
((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
|
||||
((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_sampling_time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)
|
||||
#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)
|
||||
#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)
|
||||
#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)
|
||||
#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)
|
||||
#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)
|
||||
#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)
|
||||
#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)
|
||||
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_7Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_13Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_28Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_41Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_55Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_71Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_239Cycles5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */
|
||||
|
||||
#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */
|
||||
#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */
|
||||
#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */
|
||||
|
||||
#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */
|
||||
#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */
|
||||
|
||||
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_channel_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_InjectedChannel_1 ((uint8_t)0x14)
|
||||
#define ADC_InjectedChannel_2 ((uint8_t)0x18)
|
||||
#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
|
||||
#define ADC_InjectedChannel_4 ((uint8_t)0x20)
|
||||
#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_2) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_3) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_analog_watchdog_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
|
||||
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
|
||||
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
|
||||
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
|
||||
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
|
||||
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
|
||||
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
|
||||
|
||||
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_None))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_IT_EOC ((uint16_t)0x0220)
|
||||
#define ADC_IT_AWD ((uint16_t)0x0140)
|
||||
#define ADC_IT_JEOC ((uint16_t)0x0480)
|
||||
|
||||
#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
|
||||
((IT) == ADC_IT_JEOC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_FLAG_AWD ((uint8_t)0x01)
|
||||
#define ADC_FLAG_EOC ((uint8_t)0x02)
|
||||
#define ADC_FLAG_JEOC ((uint8_t)0x04)
|
||||
#define ADC_FLAG_JSTRT ((uint8_t)0x08)
|
||||
#define ADC_FLAG_STRT ((uint8_t)0x10)
|
||||
#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))
|
||||
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
|
||||
((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
|
||||
((FLAG) == ADC_FLAG_STRT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_thresholds
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_offset
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_rank
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_regular_length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_regular_rank
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_regular_discontinuous_mode_number
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void ADC_DeInit(ADC_TypeDef* ADCx);
|
||||
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
|
||||
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
|
||||
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
|
||||
void ADC_ResetCalibration(ADC_TypeDef* ADCx);
|
||||
FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_StartCalibration(ADC_TypeDef* ADCx);
|
||||
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
|
||||
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||
void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
|
||||
uint32_t ADC_GetDualModeConversionValue(void);
|
||||
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
|
||||
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
|
||||
void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
|
||||
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
|
||||
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
|
||||
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
|
||||
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
|
||||
void ADC_TempSensorVrefintCmd(FunctionalState NewState);
|
||||
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
|
||||
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
|
||||
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
|
||||
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F10x_ADC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,308 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_bkp.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the BKP firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_bkp.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup BKP
|
||||
* @brief BKP driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ------------ BKP registers bit address in the alias region --------------- */
|
||||
#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)
|
||||
|
||||
/* --- CR Register ----*/
|
||||
|
||||
/* Alias word address of TPAL bit */
|
||||
#define CR_OFFSET (BKP_OFFSET + 0x30)
|
||||
#define TPAL_BitNumber 0x01
|
||||
#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
|
||||
|
||||
/* Alias word address of TPE bit */
|
||||
#define TPE_BitNumber 0x00
|
||||
#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
|
||||
|
||||
/* --- CSR Register ---*/
|
||||
|
||||
/* Alias word address of TPIE bit */
|
||||
#define CSR_OFFSET (BKP_OFFSET + 0x34)
|
||||
#define TPIE_BitNumber 0x02
|
||||
#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
|
||||
|
||||
/* Alias word address of TIF bit */
|
||||
#define TIF_BitNumber 0x09
|
||||
#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
|
||||
|
||||
/* Alias word address of TEF bit */
|
||||
#define TEF_BitNumber 0x08
|
||||
#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
|
||||
|
||||
/* ---------------------- BKP registers bit mask ------------------------ */
|
||||
|
||||
/* RTCCR register bit mask */
|
||||
#define RTCCR_CAL_MASK ((uint16_t)0xFF80)
|
||||
#define RTCCR_MASK ((uint16_t)0xFC7F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup BKP_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the BKP peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_DeInit(void)
|
||||
{
|
||||
RCC_BackupResetCmd(ENABLE);
|
||||
RCC_BackupResetCmd(DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the Tamper Pin active level.
|
||||
* @param BKP_TamperPinLevel: specifies the Tamper Pin active level.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg BKP_TamperPinLevel_High: Tamper pin active on high level
|
||||
* @arg BKP_TamperPinLevel_Low: Tamper pin active on low level
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
|
||||
*(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Tamper Pin activation.
|
||||
* @param NewState: new state of the Tamper Pin activation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_TamperPinCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
*(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Tamper Pin Interrupt.
|
||||
* @param NewState: new state of the Tamper Pin Interrupt.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_ITConfig(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
*(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select the RTC output source to output on the Tamper pin.
|
||||
* @param BKP_RTCOutputSource: specifies the RTC output source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
|
||||
* @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency
|
||||
* divided by 64 on the Tamper pin.
|
||||
* @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on
|
||||
* the Tamper pin.
|
||||
* @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on
|
||||
* the Tamper pin.
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
|
||||
{
|
||||
uint16_t tmpreg = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));
|
||||
tmpreg = BKP->RTCCR;
|
||||
/* Clear CCO, ASOE and ASOS bits */
|
||||
tmpreg &= RTCCR_MASK;
|
||||
|
||||
/* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
|
||||
tmpreg |= BKP_RTCOutputSource;
|
||||
/* Store the new value */
|
||||
BKP->RTCCR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets RTC Clock Calibration value.
|
||||
* @param CalibrationValue: specifies the RTC Clock Calibration value.
|
||||
* This parameter must be a number between 0 and 0x7F.
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
|
||||
{
|
||||
uint16_t tmpreg = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
|
||||
tmpreg = BKP->RTCCR;
|
||||
/* Clear CAL[6:0] bits */
|
||||
tmpreg &= RTCCR_CAL_MASK;
|
||||
/* Set CAL[6:0] bits according to CalibrationValue value */
|
||||
tmpreg |= CalibrationValue;
|
||||
/* Store the new value */
|
||||
BKP->RTCCR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes user data to the specified Data Backup Register.
|
||||
* @param BKP_DR: specifies the Data Backup Register.
|
||||
* This parameter can be BKP_DRx where x:[1, 42]
|
||||
* @param Data: data to write
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_BKP_DR(BKP_DR));
|
||||
|
||||
tmp = (uint32_t)BKP_BASE;
|
||||
tmp += BKP_DR;
|
||||
|
||||
*(__IO uint32_t *) tmp = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads data from the specified Data Backup Register.
|
||||
* @param BKP_DR: specifies the Data Backup Register.
|
||||
* This parameter can be BKP_DRx where x:[1, 42]
|
||||
* @retval The content of the specified Data Backup Register
|
||||
*/
|
||||
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_BKP_DR(BKP_DR));
|
||||
|
||||
tmp = (uint32_t)BKP_BASE;
|
||||
tmp += BKP_DR;
|
||||
|
||||
return (*(__IO uint16_t *) tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the Tamper Pin Event flag is set or not.
|
||||
* @param None
|
||||
* @retval The new state of the Tamper Pin Event flag (SET or RESET).
|
||||
*/
|
||||
FlagStatus BKP_GetFlagStatus(void)
|
||||
{
|
||||
return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears Tamper Pin Event pending flag.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_ClearFlag(void)
|
||||
{
|
||||
/* Set CTE bit to clear Tamper Pin Event flag */
|
||||
BKP->CSR |= BKP_CSR_CTE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the Tamper Pin Interrupt has occurred or not.
|
||||
* @param None
|
||||
* @retval The new state of the Tamper Pin Interrupt (SET or RESET).
|
||||
*/
|
||||
ITStatus BKP_GetITStatus(void)
|
||||
{
|
||||
return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears Tamper Pin Interrupt pending bit.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void BKP_ClearITPendingBit(void)
|
||||
{
|
||||
/* Set CTI bit to clear Tamper Pin Interrupt pending bit */
|
||||
BKP->CSR |= BKP_CSR_CTI;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,195 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_bkp.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the BKP firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_BKP_H
|
||||
#define __STM32F10x_BKP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup BKP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup Tamper_Pin_active_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BKP_TamperPinLevel_High ((uint16_t)0x0000)
|
||||
#define BKP_TamperPinLevel_Low ((uint16_t)0x0001)
|
||||
#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \
|
||||
((LEVEL) == BKP_TamperPinLevel_Low))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BKP_RTCOutputSource_None ((uint16_t)0x0000)
|
||||
#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)
|
||||
#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)
|
||||
#define BKP_RTCOutputSource_Second ((uint16_t)0x0300)
|
||||
#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \
|
||||
((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
|
||||
((SOURCE) == BKP_RTCOutputSource_Alarm) || \
|
||||
((SOURCE) == BKP_RTCOutputSource_Second))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Data_Backup_Register
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BKP_DR1 ((uint16_t)0x0004)
|
||||
#define BKP_DR2 ((uint16_t)0x0008)
|
||||
#define BKP_DR3 ((uint16_t)0x000C)
|
||||
#define BKP_DR4 ((uint16_t)0x0010)
|
||||
#define BKP_DR5 ((uint16_t)0x0014)
|
||||
#define BKP_DR6 ((uint16_t)0x0018)
|
||||
#define BKP_DR7 ((uint16_t)0x001C)
|
||||
#define BKP_DR8 ((uint16_t)0x0020)
|
||||
#define BKP_DR9 ((uint16_t)0x0024)
|
||||
#define BKP_DR10 ((uint16_t)0x0028)
|
||||
#define BKP_DR11 ((uint16_t)0x0040)
|
||||
#define BKP_DR12 ((uint16_t)0x0044)
|
||||
#define BKP_DR13 ((uint16_t)0x0048)
|
||||
#define BKP_DR14 ((uint16_t)0x004C)
|
||||
#define BKP_DR15 ((uint16_t)0x0050)
|
||||
#define BKP_DR16 ((uint16_t)0x0054)
|
||||
#define BKP_DR17 ((uint16_t)0x0058)
|
||||
#define BKP_DR18 ((uint16_t)0x005C)
|
||||
#define BKP_DR19 ((uint16_t)0x0060)
|
||||
#define BKP_DR20 ((uint16_t)0x0064)
|
||||
#define BKP_DR21 ((uint16_t)0x0068)
|
||||
#define BKP_DR22 ((uint16_t)0x006C)
|
||||
#define BKP_DR23 ((uint16_t)0x0070)
|
||||
#define BKP_DR24 ((uint16_t)0x0074)
|
||||
#define BKP_DR25 ((uint16_t)0x0078)
|
||||
#define BKP_DR26 ((uint16_t)0x007C)
|
||||
#define BKP_DR27 ((uint16_t)0x0080)
|
||||
#define BKP_DR28 ((uint16_t)0x0084)
|
||||
#define BKP_DR29 ((uint16_t)0x0088)
|
||||
#define BKP_DR30 ((uint16_t)0x008C)
|
||||
#define BKP_DR31 ((uint16_t)0x0090)
|
||||
#define BKP_DR32 ((uint16_t)0x0094)
|
||||
#define BKP_DR33 ((uint16_t)0x0098)
|
||||
#define BKP_DR34 ((uint16_t)0x009C)
|
||||
#define BKP_DR35 ((uint16_t)0x00A0)
|
||||
#define BKP_DR36 ((uint16_t)0x00A4)
|
||||
#define BKP_DR37 ((uint16_t)0x00A8)
|
||||
#define BKP_DR38 ((uint16_t)0x00AC)
|
||||
#define BKP_DR39 ((uint16_t)0x00B0)
|
||||
#define BKP_DR40 ((uint16_t)0x00B4)
|
||||
#define BKP_DR41 ((uint16_t)0x00B8)
|
||||
#define BKP_DR42 ((uint16_t)0x00BC)
|
||||
|
||||
#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \
|
||||
((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \
|
||||
((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \
|
||||
((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \
|
||||
((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \
|
||||
((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \
|
||||
((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \
|
||||
((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \
|
||||
((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \
|
||||
((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \
|
||||
((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \
|
||||
((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \
|
||||
((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \
|
||||
((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))
|
||||
|
||||
#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BKP_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void BKP_DeInit(void);
|
||||
void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
|
||||
void BKP_TamperPinCmd(FunctionalState NewState);
|
||||
void BKP_ITConfig(FunctionalState NewState);
|
||||
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
|
||||
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
|
||||
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
|
||||
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
|
||||
FlagStatus BKP_GetFlagStatus(void);
|
||||
void BKP_ClearFlag(void);
|
||||
ITStatus BKP_GetITStatus(void);
|
||||
void BKP_ClearITPendingBit(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_BKP_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,697 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_can.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the CAN firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_CAN_H
|
||||
#define __STM32F10x_CAN_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
|
||||
((PERIPH) == CAN2))
|
||||
|
||||
/**
|
||||
* @brief CAN init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum.
|
||||
It ranges from 1 to 1024. */
|
||||
|
||||
uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
|
||||
This parameter can be a value of
|
||||
@ref CAN_operating_mode */
|
||||
|
||||
uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta
|
||||
the CAN hardware is allowed to lengthen or
|
||||
shorten a bit to perform resynchronization.
|
||||
This parameter can be a value of
|
||||
@ref CAN_synchronisation_jump_width */
|
||||
|
||||
uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit
|
||||
Segment 1. This parameter can be a value of
|
||||
@ref CAN_time_quantum_in_bit_segment_1 */
|
||||
|
||||
uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit
|
||||
Segment 2.
|
||||
This parameter can be a value of
|
||||
@ref CAN_time_quantum_in_bit_segment_2 */
|
||||
|
||||
FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered
|
||||
communication mode. This parameter can be set
|
||||
either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off
|
||||
management. This parameter can be set either
|
||||
to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
|
||||
This parameter can be set either to ENABLE or
|
||||
DISABLE. */
|
||||
|
||||
FunctionalState CAN_NART; /*!< Enable or disable the no-automatic
|
||||
retransmission mode. This parameter can be
|
||||
set either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
|
||||
This parameter can be set either to ENABLE
|
||||
or DISABLE. */
|
||||
|
||||
FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
|
||||
This parameter can be set either to ENABLE
|
||||
or DISABLE. */
|
||||
} CAN_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN filter init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
|
||||
configuration, first one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
|
||||
configuration, second one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (MSBs for a 32-bit configuration,
|
||||
first one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (LSBs for a 32-bit configuration,
|
||||
second one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
|
||||
This parameter can be a value of @ref CAN_filter_FIFO */
|
||||
|
||||
uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
|
||||
|
||||
uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
|
||||
This parameter can be a value of @ref CAN_filter_mode */
|
||||
|
||||
uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
|
||||
This parameter can be a value of @ref CAN_filter_scale */
|
||||
|
||||
FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
} CAN_FilterInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN Tx message structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter can be a value between 0 to 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||
|
||||
uint8_t IDE; /*!< Specifies the type of identifier for the message that
|
||||
will be transmitted. This parameter can be a value
|
||||
of @ref CAN_identifier_type */
|
||||
|
||||
uint8_t RTR; /*!< Specifies the type of frame for the message that will
|
||||
be transmitted. This parameter can be a value of
|
||||
@ref CAN_remote_transmission_request */
|
||||
|
||||
uint8_t DLC; /*!< Specifies the length of the frame that will be
|
||||
transmitted. This parameter can be a value between
|
||||
0 to 8 */
|
||||
|
||||
uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
|
||||
to 0xFF. */
|
||||
} CanTxMsg;
|
||||
|
||||
/**
|
||||
* @brief CAN Rx message structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter can be a value between 0 to 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||
|
||||
uint8_t IDE; /*!< Specifies the type of identifier for the message that
|
||||
will be received. This parameter can be a value of
|
||||
@ref CAN_identifier_type */
|
||||
|
||||
uint8_t RTR; /*!< Specifies the type of frame for the received message.
|
||||
This parameter can be a value of
|
||||
@ref CAN_remote_transmission_request */
|
||||
|
||||
uint8_t DLC; /*!< Specifies the length of the frame that will be received.
|
||||
This parameter can be a value between 0 to 8 */
|
||||
|
||||
uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
|
||||
0xFF. */
|
||||
|
||||
uint8_t FMI; /*!< Specifies the index of the filter the message stored in
|
||||
the mailbox passes through. This parameter can be a
|
||||
value between 0 to 0xFF */
|
||||
} CanRxMsg;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_sleep_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
|
||||
#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */
|
||||
#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */
|
||||
#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */
|
||||
#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */
|
||||
|
||||
#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
|
||||
((MODE) == CAN_Mode_LoopBack)|| \
|
||||
((MODE) == CAN_Mode_Silent) || \
|
||||
((MODE) == CAN_Mode_Silent_LoopBack))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Operating_Mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */
|
||||
#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */
|
||||
#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */
|
||||
|
||||
|
||||
#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
|
||||
((MODE) == CAN_OperatingMode_Normal)|| \
|
||||
((MODE) == CAN_OperatingMode_Sleep))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Mode_Status
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
|
||||
#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_synchronisation_jump_width
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||
#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||
#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||
#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||
|
||||
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
|
||||
((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_1
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||
#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||
#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||
#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||
#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
|
||||
#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
|
||||
#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
|
||||
#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
|
||||
#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
|
||||
#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
|
||||
#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
|
||||
#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
|
||||
#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
|
||||
#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
|
||||
#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
|
||||
#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
|
||||
|
||||
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_2
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||
#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||
#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||
#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||
#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
|
||||
#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
|
||||
#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
|
||||
#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
|
||||
|
||||
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_clock_prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_number
|
||||
* @{
|
||||
*/
|
||||
#ifndef STM32F10X_CL
|
||||
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)
|
||||
#else
|
||||
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
|
||||
#endif /* STM32F10X_CL */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */
|
||||
#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */
|
||||
|
||||
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
|
||||
((MODE) == CAN_FilterMode_IdList))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_scale
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */
|
||||
#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */
|
||||
|
||||
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
|
||||
((SCALE) == CAN_FilterScale_32bit))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_FIFO
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
|
||||
#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
|
||||
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
|
||||
((FIFO) == CAN_FilterFIFO1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Start_bank_filter_for_slave_CAN
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Tx
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
|
||||
#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
|
||||
#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
|
||||
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_identifier_type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */
|
||||
#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */
|
||||
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
|
||||
((IDTYPE) == CAN_Id_Extended))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_remote_transmission_request
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */
|
||||
#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */
|
||||
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_transmit_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */
|
||||
#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
|
||||
#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
|
||||
#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_receive_FIFO_number_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
|
||||
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
|
||||
|
||||
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_sleep_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
|
||||
#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_wake_up_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
|
||||
#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Error_Code_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */
|
||||
#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
|
||||
#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */
|
||||
#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
|
||||
#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
|
||||
#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
|
||||
#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
|
||||
#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_flags
|
||||
* @{
|
||||
*/
|
||||
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
|
||||
and CAN_ClearFlag() functions. */
|
||||
/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */
|
||||
|
||||
/* Transmit Flags */
|
||||
#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
|
||||
#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
|
||||
#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
|
||||
|
||||
/* Receive Flags */
|
||||
#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
|
||||
#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */
|
||||
#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */
|
||||
#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
|
||||
#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */
|
||||
#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */
|
||||
|
||||
/* Operating Mode Flags */
|
||||
#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
|
||||
#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
|
||||
/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible.
|
||||
In this case the SLAK bit can be polled.*/
|
||||
|
||||
/* Error Flags */
|
||||
#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */
|
||||
#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */
|
||||
#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
|
||||
#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
|
||||
|
||||
#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \
|
||||
((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
|
||||
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
|
||||
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \
|
||||
((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
|
||||
((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
|
||||
((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
|
||||
((FLAG) == CAN_FLAG_SLAK ))
|
||||
|
||||
#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
|
||||
((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
|
||||
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\
|
||||
((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
|
||||
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CAN_interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
|
||||
|
||||
/* Receive Interrupts */
|
||||
#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
|
||||
#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
|
||||
#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
|
||||
#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
|
||||
#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
|
||||
#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
|
||||
|
||||
/* Operating Mode Interrupts */
|
||||
#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
|
||||
#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
|
||||
|
||||
/* Error Interrupts */
|
||||
#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
|
||||
#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
|
||||
#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
|
||||
#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
|
||||
#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
|
||||
|
||||
/* Flags named as Interrupts : kept only for FW compatibility */
|
||||
#define CAN_IT_RQCP0 CAN_IT_TME
|
||||
#define CAN_IT_RQCP1 CAN_IT_TME
|
||||
#define CAN_IT_RQCP2 CAN_IT_TME
|
||||
|
||||
|
||||
#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
|
||||
((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
|
||||
((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
|
||||
((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
|
||||
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
||||
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
||||
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
|
||||
|
||||
#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
|
||||
((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
|
||||
((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
|
||||
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
||||
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
||||
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Legacy
|
||||
* @{
|
||||
*/
|
||||
#define CANINITFAILED CAN_InitStatus_Failed
|
||||
#define CANINITOK CAN_InitStatus_Success
|
||||
#define CAN_FilterFIFO0 CAN_Filter_FIFO0
|
||||
#define CAN_FilterFIFO1 CAN_Filter_FIFO1
|
||||
#define CAN_ID_STD CAN_Id_Standard
|
||||
#define CAN_ID_EXT CAN_Id_Extended
|
||||
#define CAN_RTR_DATA CAN_RTR_Data
|
||||
#define CAN_RTR_REMOTE CAN_RTR_Remote
|
||||
#define CANTXFAILE CAN_TxStatus_Failed
|
||||
#define CANTXOK CAN_TxStatus_Ok
|
||||
#define CANTXPENDING CAN_TxStatus_Pending
|
||||
#define CAN_NO_MB CAN_TxStatus_NoMailBox
|
||||
#define CANSLEEPFAILED CAN_Sleep_Failed
|
||||
#define CANSLEEPOK CAN_Sleep_Ok
|
||||
#define CANWAKEUPFAILED CAN_WakeUp_Failed
|
||||
#define CANWAKEUPOK CAN_WakeUp_Ok
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
/* Function used to set the CAN configuration to the default reset state *****/
|
||||
void CAN_DeInit(CAN_TypeDef* CANx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
|
||||
void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
|
||||
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
|
||||
void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
|
||||
void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
|
||||
void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
|
||||
|
||||
/* Transmit functions *********************************************************/
|
||||
uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
|
||||
uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
|
||||
void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
|
||||
|
||||
/* Receive functions **********************************************************/
|
||||
void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
|
||||
void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
|
||||
uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
|
||||
|
||||
|
||||
/* Operation modes functions **************************************************/
|
||||
uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
|
||||
uint8_t CAN_Sleep(CAN_TypeDef* CANx);
|
||||
uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
|
||||
|
||||
/* Error management functions *************************************************/
|
||||
uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
|
||||
uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
|
||||
uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
|
||||
FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
|
||||
void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
|
||||
ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
|
||||
void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_CAN_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,433 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_cec.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the CEC firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_cec.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CEC
|
||||
* @brief CEC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ------------ CEC registers bit address in the alias region ----------- */
|
||||
#define CEC_OFFSET (CEC_BASE - PERIPH_BASE)
|
||||
|
||||
/* --- CFGR Register ---*/
|
||||
|
||||
/* Alias word address of PE bit */
|
||||
#define CFGR_OFFSET (CEC_OFFSET + 0x00)
|
||||
#define PE_BitNumber 0x00
|
||||
#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))
|
||||
|
||||
/* Alias word address of IE bit */
|
||||
#define IE_BitNumber 0x01
|
||||
#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))
|
||||
|
||||
/* --- CSR Register ---*/
|
||||
|
||||
/* Alias word address of TSOM bit */
|
||||
#define CSR_OFFSET (CEC_OFFSET + 0x10)
|
||||
#define TSOM_BitNumber 0x00
|
||||
#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
|
||||
|
||||
/* Alias word address of TEOM bit */
|
||||
#define TEOM_BitNumber 0x01
|
||||
#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
|
||||
|
||||
#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */
|
||||
#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the CEC peripheral registers to their default reset
|
||||
* values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_DeInit(void)
|
||||
{
|
||||
/* Enable CEC reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);
|
||||
/* Release CEC from reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initializes the CEC peripheral according to the specified
|
||||
* parameters in the CEC_InitStruct.
|
||||
* @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that
|
||||
* contains the configuration information for the specified
|
||||
* CEC peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
|
||||
{
|
||||
uint16_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode));
|
||||
assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));
|
||||
|
||||
/*---------------------------- CEC CFGR Configuration -----------------*/
|
||||
/* Get the CEC CFGR value */
|
||||
tmpreg = CEC->CFGR;
|
||||
|
||||
/* Clear BTEM and BPEM bits */
|
||||
tmpreg &= CFGR_CLEAR_Mask;
|
||||
|
||||
/* Configure CEC: Bit Timing Error and Bit Period Error */
|
||||
tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);
|
||||
|
||||
/* Write to CEC CFGR register*/
|
||||
CEC->CFGR = tmpreg;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified CEC peripheral.
|
||||
* @param NewState: new state of the CEC peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_Cmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;
|
||||
|
||||
if(NewState == DISABLE)
|
||||
{
|
||||
/* Wait until the PE bit is cleared by hardware (Idle Line detected) */
|
||||
while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)
|
||||
{
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the CEC interrupt.
|
||||
* @param NewState: new state of the CEC interrupt.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_ITConfig(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Defines the Own Address of the CEC device.
|
||||
* @param CEC_OwnAddress: The CEC own address
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
|
||||
|
||||
/* Set the CEC own address */
|
||||
CEC->OAR = CEC_OwnAddress;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the CEC prescaler value.
|
||||
* @param CEC_Prescaler: CEC prescaler new value
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_SetPrescaler(uint16_t CEC_Prescaler)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_PRESCALER(CEC_Prescaler));
|
||||
|
||||
/* Set the Prescaler value*/
|
||||
CEC->PRES = CEC_Prescaler;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Transmits single data through the CEC peripheral.
|
||||
* @param Data: the data to transmit.
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_SendDataByte(uint8_t Data)
|
||||
{
|
||||
/* Transmit Data */
|
||||
CEC->TXD = Data ;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Returns the most recent received data by the CEC peripheral.
|
||||
* @param None
|
||||
* @retval The received data.
|
||||
*/
|
||||
uint8_t CEC_ReceiveDataByte(void)
|
||||
{
|
||||
/* Receive Data */
|
||||
return (uint8_t)(CEC->RXD);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Starts a new message.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_StartOfMessage(void)
|
||||
{
|
||||
/* Starts of new message */
|
||||
*(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Transmits message with or without an EOM bit.
|
||||
* @param NewState: new state of the CEC Tx End Of Message.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_EndOfMessageCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* The data byte will be transmitted with or without an EOM bit*/
|
||||
*(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the CEC flag status
|
||||
* @param CEC_FLAG: specifies the CEC flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_FLAG_BTE: Bit Timing Error
|
||||
* @arg CEC_FLAG_BPE: Bit Period Error
|
||||
* @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error
|
||||
* @arg CEC_FLAG_SBE: Start Bit Error
|
||||
* @arg CEC_FLAG_ACKE: Block Acknowledge Error
|
||||
* @arg CEC_FLAG_LINE: Line Error
|
||||
* @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error
|
||||
* @arg CEC_FLAG_TEOM: Tx End Of Message
|
||||
* @arg CEC_FLAG_TERR: Tx Error
|
||||
* @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
|
||||
* @arg CEC_FLAG_RSOM: Rx Start Of Message
|
||||
* @arg CEC_FLAG_REOM: Rx End Of Message
|
||||
* @arg CEC_FLAG_RERR: Rx Error
|
||||
* @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
|
||||
* @retval The new state of CEC_FLAG (SET or RESET)
|
||||
*/
|
||||
FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
uint32_t cecreg = 0, cecbase = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
|
||||
|
||||
/* Get the CEC peripheral base address */
|
||||
cecbase = (uint32_t)(CEC_BASE);
|
||||
|
||||
/* Read flag register index */
|
||||
cecreg = CEC_FLAG >> 28;
|
||||
|
||||
/* Get bit[23:0] of the flag */
|
||||
CEC_FLAG &= FLAG_Mask;
|
||||
|
||||
if(cecreg != 0)
|
||||
{
|
||||
/* Flag in CEC ESR Register */
|
||||
CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);
|
||||
|
||||
/* Get the CEC ESR register address */
|
||||
cecbase += 0xC;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get the CEC CSR register address */
|
||||
cecbase += 0x10;
|
||||
}
|
||||
|
||||
if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
/* CEC_FLAG is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* CEC_FLAG is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
/* Return the CEC_FLAG status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the CEC's pending flags.
|
||||
* @param CEC_FLAG: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg CEC_FLAG_TERR: Tx Error
|
||||
* @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
|
||||
* @arg CEC_FLAG_RSOM: Rx Start Of Message
|
||||
* @arg CEC_FLAG_REOM: Rx End Of Message
|
||||
* @arg CEC_FLAG_RERR: Rx Error
|
||||
* @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_ClearFlag(uint32_t CEC_FLAG)
|
||||
{
|
||||
uint32_t tmp = 0x0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
|
||||
|
||||
tmp = CEC->CSR & 0x2;
|
||||
|
||||
/* Clear the selected CEC flags */
|
||||
CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified CEC interrupt has occurred or not.
|
||||
* @param CEC_IT: specifies the CEC interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IT_TERR: Tx Error
|
||||
* @arg CEC_IT_TBTF: Tx Block Transfer Finished
|
||||
* @arg CEC_IT_RERR: Rx Error
|
||||
* @arg CEC_IT_RBTF: Rx Block Transfer Finished
|
||||
* @retval The new state of CEC_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus CEC_GetITStatus(uint8_t CEC_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t enablestatus = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_GET_IT(CEC_IT));
|
||||
|
||||
/* Get the CEC IT enable bit status */
|
||||
enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;
|
||||
|
||||
/* Check the status of the specified CEC interrupt */
|
||||
if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)
|
||||
{
|
||||
/* CEC_IT is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* CEC_IT is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the CEC_IT status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the CEC's interrupt pending bits.
|
||||
* @param CEC_IT: specifies the CEC interrupt pending bit to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg CEC_IT_TERR: Tx Error
|
||||
* @arg CEC_IT_TBTF: Tx Block Transfer Finished
|
||||
* @arg CEC_IT_RERR: Rx Error
|
||||
* @arg CEC_IT_RBTF: Rx Block Transfer Finished
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_ClearITPendingBit(uint16_t CEC_IT)
|
||||
{
|
||||
uint32_t tmp = 0x0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_GET_IT(CEC_IT));
|
||||
|
||||
tmp = CEC->CSR & 0x2;
|
||||
|
||||
/* Clear the selected CEC interrupt pending bits */
|
||||
CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,210 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_cec.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the CEC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_CEC_H
|
||||
#define __STM32F10x_CEC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CEC Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode.
|
||||
This parameter can be a value of @ref CEC_BitTiming_Mode */
|
||||
uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode.
|
||||
This parameter can be a value of @ref CEC_BitPeriod_Mode */
|
||||
}CEC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BitTiming_Mode
|
||||
* @{
|
||||
*/
|
||||
#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */
|
||||
#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */
|
||||
|
||||
#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \
|
||||
((MODE) == CEC_BitTimingErrFreeMode))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BitPeriod_Mode
|
||||
* @{
|
||||
*/
|
||||
#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */
|
||||
#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */
|
||||
|
||||
#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \
|
||||
((MODE) == CEC_BitPeriodFlexibleMode))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IT_TERR CEC_CSR_TERR
|
||||
#define CEC_IT_TBTRF CEC_CSR_TBTRF
|
||||
#define CEC_IT_RERR CEC_CSR_RERR
|
||||
#define CEC_IT_RBTF CEC_CSR_RBTF
|
||||
#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \
|
||||
((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_Own_Address
|
||||
* @{
|
||||
*/
|
||||
#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ESR register flags
|
||||
*/
|
||||
#define CEC_FLAG_BTE ((uint32_t)0x10010000)
|
||||
#define CEC_FLAG_BPE ((uint32_t)0x10020000)
|
||||
#define CEC_FLAG_RBTFE ((uint32_t)0x10040000)
|
||||
#define CEC_FLAG_SBE ((uint32_t)0x10080000)
|
||||
#define CEC_FLAG_ACKE ((uint32_t)0x10100000)
|
||||
#define CEC_FLAG_LINE ((uint32_t)0x10200000)
|
||||
#define CEC_FLAG_TBTFE ((uint32_t)0x10400000)
|
||||
|
||||
/**
|
||||
* @brief CSR register flags
|
||||
*/
|
||||
#define CEC_FLAG_TEOM ((uint32_t)0x00000002)
|
||||
#define CEC_FLAG_TERR ((uint32_t)0x00000004)
|
||||
#define CEC_FLAG_TBTRF ((uint32_t)0x00000008)
|
||||
#define CEC_FLAG_RSOM ((uint32_t)0x00000010)
|
||||
#define CEC_FLAG_REOM ((uint32_t)0x00000020)
|
||||
#define CEC_FLAG_RERR ((uint32_t)0x00000040)
|
||||
#define CEC_FLAG_RBTF ((uint32_t)0x00000080)
|
||||
|
||||
#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))
|
||||
|
||||
#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \
|
||||
((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \
|
||||
((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \
|
||||
((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \
|
||||
((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \
|
||||
((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \
|
||||
((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
void CEC_DeInit(void);
|
||||
void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
|
||||
void CEC_Cmd(FunctionalState NewState);
|
||||
void CEC_ITConfig(FunctionalState NewState);
|
||||
void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
|
||||
void CEC_SetPrescaler(uint16_t CEC_Prescaler);
|
||||
void CEC_SendDataByte(uint8_t Data);
|
||||
uint8_t CEC_ReceiveDataByte(void);
|
||||
void CEC_StartOfMessage(void);
|
||||
void CEC_EndOfMessageCmd(FunctionalState NewState);
|
||||
FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG);
|
||||
void CEC_ClearFlag(uint32_t CEC_FLAG);
|
||||
ITStatus CEC_GetITStatus(uint8_t CEC_IT);
|
||||
void CEC_ClearITPendingBit(uint16_t CEC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_CEC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,160 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_crc.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the CRC firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_crc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC
|
||||
* @brief CRC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Resets the CRC Data register (DR).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_ResetDR(void)
|
||||
{
|
||||
/* Reset CRC generator */
|
||||
CRC->CR = CRC_CR_RESET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Computes the 32-bit CRC of a given data word(32-bit).
|
||||
* @param Data: data word(32-bit) to compute its CRC
|
||||
* @retval 32-bit CRC
|
||||
*/
|
||||
uint32_t CRC_CalcCRC(uint32_t Data)
|
||||
{
|
||||
CRC->DR = Data;
|
||||
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
|
||||
* @param pBuffer: pointer to the buffer containing the data to be computed
|
||||
* @param BufferLength: length of the buffer to be computed
|
||||
* @retval 32-bit CRC
|
||||
*/
|
||||
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t index = 0;
|
||||
|
||||
for(index = 0; index < BufferLength; index++)
|
||||
{
|
||||
CRC->DR = pBuffer[index];
|
||||
}
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the current CRC value.
|
||||
* @param None
|
||||
* @retval 32-bit CRC
|
||||
*/
|
||||
uint32_t CRC_GetCRC(void)
|
||||
{
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stores a 8-bit data in the Independent Data(ID) register.
|
||||
* @param IDValue: 8-bit value to be stored in the ID register
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_SetIDRegister(uint8_t IDValue)
|
||||
{
|
||||
CRC->IDR = IDValue;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the 8-bit data stored in the Independent Data(ID) register
|
||||
* @param None
|
||||
* @retval 8-bit value of the ID register
|
||||
*/
|
||||
uint8_t CRC_GetIDRegister(void)
|
||||
{
|
||||
return (CRC->IDR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,94 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_crc.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the CRC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_CRC_H
|
||||
#define __STM32F10x_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void CRC_ResetDR(void);
|
||||
uint32_t CRC_CalcCRC(uint32_t Data);
|
||||
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
|
||||
uint32_t CRC_GetCRC(void);
|
||||
void CRC_SetIDRegister(uint8_t IDValue);
|
||||
uint8_t CRC_GetIDRegister(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_CRC_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,571 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_dac.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the DAC firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_dac.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC
|
||||
* @brief DAC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* CR register Mask */
|
||||
#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)
|
||||
|
||||
/* DAC Dual Channels SWTRIG masks */
|
||||
#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
|
||||
#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
|
||||
|
||||
/* DHR registers offsets */
|
||||
#define DHR12R1_OFFSET ((uint32_t)0x00000008)
|
||||
#define DHR12R2_OFFSET ((uint32_t)0x00000014)
|
||||
#define DHR12RD_OFFSET ((uint32_t)0x00000020)
|
||||
|
||||
/* DOR register offset */
|
||||
#define DOR_OFFSET ((uint32_t)0x0000002C)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the DAC peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DeInit(void)
|
||||
{
|
||||
/* Enable DAC reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
|
||||
/* Release DAC from reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the DAC peripheral according to the specified
|
||||
* parameters in the DAC_InitStruct.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
|
||||
* contains the configuration information for the specified DAC channel.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg1 = 0, tmpreg2 = 0;
|
||||
/* Check the DAC parameters */
|
||||
assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
|
||||
assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
|
||||
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
|
||||
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
|
||||
/*---------------------------- DAC CR Configuration --------------------------*/
|
||||
/* Get the DAC CR value */
|
||||
tmpreg1 = DAC->CR;
|
||||
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
|
||||
tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
|
||||
/* Configure for the selected DAC channel: buffer output, trigger, wave generation,
|
||||
mask/amplitude for wave generation */
|
||||
/* Set TSELx and TENx bits according to DAC_Trigger value */
|
||||
/* Set WAVEx bits according to DAC_WaveGeneration value */
|
||||
/* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
|
||||
/* Set BOFFx bit according to DAC_OutputBuffer value */
|
||||
tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
|
||||
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
|
||||
/* Calculate CR register value depending on DAC_Channel */
|
||||
tmpreg1 |= tmpreg2 << DAC_Channel;
|
||||
/* Write to DAC CR */
|
||||
DAC->CR = tmpreg1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each DAC_InitStruct member with its default value.
|
||||
* @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
|
||||
{
|
||||
/*--------------- Reset DAC init structure parameters values -----------------*/
|
||||
/* Initialize the DAC_Trigger member */
|
||||
DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
|
||||
/* Initialize the DAC_WaveGeneration member */
|
||||
DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
|
||||
/* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
|
||||
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
|
||||
/* Initialize the DAC_OutputBuffer member */
|
||||
DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC channel.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param NewState: new state of the DAC channel.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC channel */
|
||||
DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC channel */
|
||||
DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel);
|
||||
}
|
||||
}
|
||||
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC interrupts.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
|
||||
* This parameter can be the following values:
|
||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||
* @param NewState: new state of the specified DAC interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
assert_param(IS_DAC_IT(DAC_IT));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC interrupts */
|
||||
DAC->CR |= (DAC_IT << DAC_Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC interrupts */
|
||||
DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC channel DMA request.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param NewState: new state of the selected DAC channel DMA request.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC channel DMA request */
|
||||
DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC channel DMA request */
|
||||
DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel software trigger.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param NewState: new state of the selected DAC channel software trigger.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable software trigger for the selected DAC channel */
|
||||
DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable software trigger for the selected DAC channel */
|
||||
DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables simultaneously the two DAC channels software
|
||||
* triggers.
|
||||
* @param NewState: new state of the DAC channels software triggers.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable software trigger for both DAC channels */
|
||||
DAC->SWTRIGR |= DUAL_SWTRIG_SET ;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable software trigger for both DAC channels */
|
||||
DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel wave generation.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_Wave: Specifies the wave type to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Wave_Noise: noise wave generation
|
||||
* @arg DAC_Wave_Triangle: triangle wave generation
|
||||
* @param NewState: new state of the selected DAC channel wave generation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_WAVE(DAC_Wave));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected wave generation for the selected DAC channel */
|
||||
DAC->CR |= DAC_Wave << DAC_Channel;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected wave generation for the selected DAC channel */
|
||||
DAC->CR &= ~(DAC_Wave << DAC_Channel);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for DAC channel1.
|
||||
* @param DAC_Align: Specifies the data alignment for DAC channel1.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @param Data : Data to be loaded in the selected data holding register.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||
assert_param(IS_DAC_DATA(Data));
|
||||
|
||||
tmp = (uint32_t)DAC_BASE;
|
||||
tmp += DHR12R1_OFFSET + DAC_Align;
|
||||
|
||||
/* Set the DAC channel1 selected data holding register */
|
||||
*(__IO uint32_t *) tmp = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for DAC channel2.
|
||||
* @param DAC_Align: Specifies the data alignment for DAC channel2.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @param Data : Data to be loaded in the selected data holding register.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||
assert_param(IS_DAC_DATA(Data));
|
||||
|
||||
tmp = (uint32_t)DAC_BASE;
|
||||
tmp += DHR12R2_OFFSET + DAC_Align;
|
||||
|
||||
/* Set the DAC channel2 selected data holding register */
|
||||
*(__IO uint32_t *)tmp = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for dual channel
|
||||
* DAC.
|
||||
* @param DAC_Align: Specifies the data alignment for dual channel DAC.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @param Data2: Data for DAC Channel2 to be loaded in the selected data
|
||||
* holding register.
|
||||
* @param Data1: Data for DAC Channel1 to be loaded in the selected data
|
||||
* holding register.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
|
||||
{
|
||||
uint32_t data = 0, tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||
assert_param(IS_DAC_DATA(Data1));
|
||||
assert_param(IS_DAC_DATA(Data2));
|
||||
|
||||
/* Calculate and set dual DAC data holding register value */
|
||||
if (DAC_Align == DAC_Align_8b_R)
|
||||
{
|
||||
data = ((uint32_t)Data2 << 8) | Data1;
|
||||
}
|
||||
else
|
||||
{
|
||||
data = ((uint32_t)Data2 << 16) | Data1;
|
||||
}
|
||||
|
||||
tmp = (uint32_t)DAC_BASE;
|
||||
tmp += DHR12RD_OFFSET + DAC_Align;
|
||||
|
||||
/* Set the dual DAC selected data holding register */
|
||||
*(__IO uint32_t *)tmp = data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
|
||||
tmp = (uint32_t) DAC_BASE ;
|
||||
tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
|
||||
|
||||
/* Returns the DAC channel data output register value */
|
||||
return (uint16_t) (*(__IO uint32_t*) tmp);
|
||||
}
|
||||
|
||||
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
||||
/**
|
||||
* @brief Checks whether the specified DAC flag is set or not.
|
||||
* @param DAC_Channel: thee selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_FLAG: specifies the flag to check.
|
||||
* This parameter can be only of the following value:
|
||||
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
|
||||
* @retval The new state of DAC_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_FLAG(DAC_FLAG));
|
||||
|
||||
/* Check the status of the specified DAC flag */
|
||||
if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
|
||||
{
|
||||
/* DAC_FLAG is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DAC_FLAG is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the DAC_FLAG status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DAC channelx's pending flags.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_FLAG: specifies the flag to clear.
|
||||
* This parameter can be of the following value:
|
||||
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_FLAG(DAC_FLAG));
|
||||
|
||||
/* Clear the selected DAC flags */
|
||||
DAC->SR = (DAC_FLAG << DAC_Channel);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DAC interrupt has occurred or not.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_IT: specifies the DAC interrupt source to check.
|
||||
* This parameter can be the following values:
|
||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||
* @retval The new state of DAC_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t enablestatus = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_IT(DAC_IT));
|
||||
|
||||
/* Get the DAC_IT enable bit status */
|
||||
enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
|
||||
|
||||
/* Check the status of the specified DAC interrupt */
|
||||
if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
|
||||
{
|
||||
/* DAC_IT is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DAC_IT is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the DAC_IT status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DAC channelx's interrupt pending bits.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_IT: specifies the DAC interrupt pending bit to clear.
|
||||
* This parameter can be the following values:
|
||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_IT(DAC_IT));
|
||||
|
||||
/* Clear the selected DAC interrupt pending bits */
|
||||
DAC->SR = (DAC_IT << DAC_Channel);
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,317 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_dac.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the DAC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_DAC_H
|
||||
#define __STM32F10x_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DAC Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_trigger_selection */
|
||||
|
||||
uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
|
||||
are generated, or whether no wave is generated.
|
||||
This parameter can be a value of @ref DAC_wave_generation */
|
||||
|
||||
uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
|
||||
the maximum amplitude triangle generation for the DAC channel.
|
||||
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
|
||||
|
||||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_output_buffer */
|
||||
}DAC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_trigger_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
|
||||
only in High-density devices*/
|
||||
#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
|
||||
only in Connectivity line, Medium-density and Low-density Value Line devices */
|
||||
#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel
|
||||
only in Medium-density and Low-density Value Line devices*/
|
||||
#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
|
||||
((TRIGGER) == DAC_Trigger_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T8_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T5_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_Ext_IT9) || \
|
||||
((TRIGGER) == DAC_Trigger_Software))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_wave_generation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
|
||||
#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
|
||||
#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
|
||||
#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
|
||||
((WAVE) == DAC_WaveGeneration_Noise) || \
|
||||
((WAVE) == DAC_WaveGeneration_Triangle))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_lfsrunmask_triangleamplitude
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||
#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
|
||||
#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
|
||||
#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
|
||||
#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
|
||||
#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
|
||||
#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
|
||||
#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
|
||||
#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
|
||||
#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
|
||||
#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
|
||||
#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
|
||||
#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
|
||||
|
||||
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_1) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_3) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_7) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_15) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_31) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_63) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_127) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_255) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_511) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_1023) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_2047) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_4095))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_output_buffer
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
|
||||
#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
|
||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
|
||||
((STATE) == DAC_OutputBuffer_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Channel_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Channel_1 ((uint32_t)0x00000000)
|
||||
#define DAC_Channel_2 ((uint32_t)0x00000010)
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
|
||||
((CHANNEL) == DAC_Channel_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data_alignment
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Align_12b_R ((uint32_t)0x00000000)
|
||||
#define DAC_Align_12b_L ((uint32_t)0x00000004)
|
||||
#define DAC_Align_8b_R ((uint32_t)0x00000008)
|
||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
|
||||
((ALIGN) == DAC_Align_12b_L) || \
|
||||
((ALIGN) == DAC_Align_8b_R))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_wave_generation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Wave_Noise ((uint32_t)0x00000040)
|
||||
#define DAC_Wave_Triangle ((uint32_t)0x00000080)
|
||||
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
|
||||
((WAVE) == DAC_Wave_Triangle))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
||||
/** @defgroup DAC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_IT_DMAUDR ((uint32_t)0x00002000)
|
||||
#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
|
||||
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void DAC_DeInit(void);
|
||||
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
|
||||
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
|
||||
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
||||
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
|
||||
#endif
|
||||
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
|
||||
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
|
||||
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
|
||||
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
|
||||
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
|
||||
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
|
||||
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
||||
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
|
||||
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
|
||||
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
|
||||
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F10x_DAC_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,162 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_dbgmcu.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the DBGMCU firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_dbgmcu.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU
|
||||
* @brief DBGMCU driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the device revision identifier.
|
||||
* @param None
|
||||
* @retval Device revision identifier
|
||||
*/
|
||||
uint32_t DBGMCU_GetREVID(void)
|
||||
{
|
||||
return(DBGMCU->IDCODE >> 16);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device identifier.
|
||||
* @param None
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t DBGMCU_GetDEVID(void)
|
||||
{
|
||||
return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the specified peripheral and low power mode behavior
|
||||
* when the MCU under Debug mode.
|
||||
* @param DBGMCU_Periph: specifies the peripheral and low power mode.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
|
||||
* @arg DBGMCU_STOP: Keep debugger connection during STOP mode
|
||||
* @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
|
||||
* @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
|
||||
* @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
|
||||
* @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
|
||||
* @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
|
||||
* @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
|
||||
* @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
|
||||
* @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
|
||||
* @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted
|
||||
* @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
|
||||
* @param NewState: new state of the specified peripheral in Debug mode.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
DBGMCU->CR |= DBGMCU_Periph;
|
||||
}
|
||||
else
|
||||
{
|
||||
DBGMCU->CR &= ~DBGMCU_Periph;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,119 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_dbgmcu.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the DBGMCU
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_DBGMCU_H
|
||||
#define __STM32F10x_DBGMCU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DBGMCU
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DBGMCU_SLEEP ((uint32_t)0x00000001)
|
||||
#define DBGMCU_STOP ((uint32_t)0x00000002)
|
||||
#define DBGMCU_STANDBY ((uint32_t)0x00000004)
|
||||
#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)
|
||||
#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)
|
||||
#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400)
|
||||
#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800)
|
||||
#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000)
|
||||
#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000)
|
||||
#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000)
|
||||
#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)
|
||||
#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)
|
||||
#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000)
|
||||
#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000)
|
||||
#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000)
|
||||
#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000)
|
||||
#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)
|
||||
#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000)
|
||||
#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000)
|
||||
#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000)
|
||||
#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000)
|
||||
#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000)
|
||||
#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000)
|
||||
#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000)
|
||||
#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000)
|
||||
#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000)
|
||||
|
||||
#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint32_t DBGMCU_GetREVID(void);
|
||||
uint32_t DBGMCU_GetDEVID(void);
|
||||
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_DBGMCU_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,714 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_dma.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the DMA firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_dma.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA
|
||||
* @brief DMA driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* DMA1 Channelx interrupt pending bit masks */
|
||||
#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
|
||||
#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
|
||||
#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
|
||||
#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
|
||||
#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
|
||||
#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
|
||||
#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
|
||||
|
||||
/* DMA2 Channelx interrupt pending bit masks */
|
||||
#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
|
||||
#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
|
||||
#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
|
||||
#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
|
||||
#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
|
||||
|
||||
/* DMA2 FLAG mask */
|
||||
#define FLAG_Mask ((uint32_t)0x10000000)
|
||||
|
||||
/* DMA registers Masks */
|
||||
#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the DMAy Channelx registers to their default reset
|
||||
* values.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
|
||||
/* Disable the selected DMAy Channelx */
|
||||
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
|
||||
|
||||
/* Reset DMAy Channelx control register */
|
||||
DMAy_Channelx->CCR = 0;
|
||||
|
||||
/* Reset DMAy Channelx remaining bytes register */
|
||||
DMAy_Channelx->CNDTR = 0;
|
||||
|
||||
/* Reset DMAy Channelx peripheral address register */
|
||||
DMAy_Channelx->CPAR = 0;
|
||||
|
||||
/* Reset DMAy Channelx memory address register */
|
||||
DMAy_Channelx->CMAR = 0;
|
||||
|
||||
if (DMAy_Channelx == DMA1_Channel1)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel1 */
|
||||
DMA1->IFCR |= DMA1_Channel1_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel2)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel2 */
|
||||
DMA1->IFCR |= DMA1_Channel2_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel3)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel3 */
|
||||
DMA1->IFCR |= DMA1_Channel3_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel4)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel4 */
|
||||
DMA1->IFCR |= DMA1_Channel4_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel5)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel5 */
|
||||
DMA1->IFCR |= DMA1_Channel5_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel6)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel6 */
|
||||
DMA1->IFCR |= DMA1_Channel6_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel7)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel7 */
|
||||
DMA1->IFCR |= DMA1_Channel7_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA2_Channel1)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel1 */
|
||||
DMA2->IFCR |= DMA2_Channel1_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA2_Channel2)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel2 */
|
||||
DMA2->IFCR |= DMA2_Channel2_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA2_Channel3)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel3 */
|
||||
DMA2->IFCR |= DMA2_Channel3_IT_Mask;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA2_Channel4)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel4 */
|
||||
DMA2->IFCR |= DMA2_Channel4_IT_Mask;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (DMAy_Channelx == DMA2_Channel5)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel5 */
|
||||
DMA2->IFCR |= DMA2_Channel5_IT_Mask;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the DMAy Channelx according to the specified
|
||||
* parameters in the DMA_InitStruct.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
|
||||
* contains the configuration information for the specified DMA Channel.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
|
||||
assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
|
||||
assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
|
||||
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
|
||||
assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
|
||||
assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
|
||||
assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
|
||||
assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
|
||||
|
||||
/*--------------------------- DMAy Channelx CCR Configuration -----------------*/
|
||||
/* Get the DMAy_Channelx CCR value */
|
||||
tmpreg = DMAy_Channelx->CCR;
|
||||
/* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
|
||||
tmpreg &= CCR_CLEAR_Mask;
|
||||
/* Configure DMAy Channelx: data transfer, data size, priority level and mode */
|
||||
/* Set DIR bit according to DMA_DIR value */
|
||||
/* Set CIRC bit according to DMA_Mode value */
|
||||
/* Set PINC bit according to DMA_PeripheralInc value */
|
||||
/* Set MINC bit according to DMA_MemoryInc value */
|
||||
/* Set PSIZE bits according to DMA_PeripheralDataSize value */
|
||||
/* Set MSIZE bits according to DMA_MemoryDataSize value */
|
||||
/* Set PL bits according to DMA_Priority value */
|
||||
/* Set the MEM2MEM bit according to DMA_M2M value */
|
||||
tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
|
||||
DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
|
||||
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
|
||||
DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
|
||||
|
||||
/* Write to DMAy Channelx CCR */
|
||||
DMAy_Channelx->CCR = tmpreg;
|
||||
|
||||
/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
|
||||
/* Write to DMAy Channelx CNDTR */
|
||||
DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
|
||||
|
||||
/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
|
||||
/* Write to DMAy Channelx CPAR */
|
||||
DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
|
||||
|
||||
/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
|
||||
/* Write to DMAy Channelx CMAR */
|
||||
DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each DMA_InitStruct member with its default value.
|
||||
* @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
|
||||
{
|
||||
/*-------------- Reset DMA init structure parameters values ------------------*/
|
||||
/* Initialize the DMA_PeripheralBaseAddr member */
|
||||
DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
|
||||
/* Initialize the DMA_MemoryBaseAddr member */
|
||||
DMA_InitStruct->DMA_MemoryBaseAddr = 0;
|
||||
/* Initialize the DMA_DIR member */
|
||||
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
|
||||
/* Initialize the DMA_BufferSize member */
|
||||
DMA_InitStruct->DMA_BufferSize = 0;
|
||||
/* Initialize the DMA_PeripheralInc member */
|
||||
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
||||
/* Initialize the DMA_MemoryInc member */
|
||||
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
|
||||
/* Initialize the DMA_PeripheralDataSize member */
|
||||
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
||||
/* Initialize the DMA_MemoryDataSize member */
|
||||
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
|
||||
/* Initialize the DMA_Mode member */
|
||||
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
|
||||
/* Initialize the DMA_Priority member */
|
||||
DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
|
||||
/* Initialize the DMA_M2M member */
|
||||
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DMAy Channelx.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @param NewState: new state of the DMAy Channelx.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DMAy Channelx */
|
||||
DMAy_Channelx->CCR |= DMA_CCR1_EN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DMAy Channelx */
|
||||
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DMAy Channelx interrupts.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @param DMA_IT: specifies the DMA interrupts sources to be enabled
|
||||
* or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @param NewState: new state of the specified DMA interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
assert_param(IS_DMA_CONFIG_IT(DMA_IT));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DMA interrupts */
|
||||
DMAy_Channelx->CCR |= DMA_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DMA interrupts */
|
||||
DMAy_Channelx->CCR &= ~DMA_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the number of data units in the current DMAy Channelx transfer.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @param DataNumber: The number of data units in the current DMAy Channelx
|
||||
* transfer.
|
||||
* @note This function can only be used when the DMAy_Channelx is disabled.
|
||||
* @retval None.
|
||||
*/
|
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
|
||||
/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
|
||||
/* Write to DMAy Channelx CNDTR */
|
||||
DMAy_Channelx->CNDTR = DataNumber;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the number of remaining data units in the current
|
||||
* DMAy Channelx transfer.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @retval The number of remaining data units in the current DMAy Channelx
|
||||
* transfer.
|
||||
*/
|
||||
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
/* Return the number of remaining data units for DMAy Channelx */
|
||||
return ((uint16_t)(DMAy_Channelx->CNDTR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DMAy Channelx flag is set or not.
|
||||
* @param DMAy_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
|
||||
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
|
||||
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
|
||||
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
|
||||
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
|
||||
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
|
||||
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
|
||||
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
|
||||
* @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
|
||||
* @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
|
||||
* @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
|
||||
* @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
|
||||
* @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
|
||||
* @retval The new state of DMAy_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
|
||||
|
||||
/* Calculate the used DMAy */
|
||||
if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
|
||||
{
|
||||
/* Get DMA2 ISR register value */
|
||||
tmpreg = DMA2->ISR ;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get DMA1 ISR register value */
|
||||
tmpreg = DMA1->ISR ;
|
||||
}
|
||||
|
||||
/* Check the status of the specified DMAy flag */
|
||||
if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
/* DMAy_FLAG is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DMAy_FLAG is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
/* Return the DMAy_FLAG status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DMAy Channelx's pending flags.
|
||||
* @param DMAy_FLAG: specifies the flag to clear.
|
||||
* This parameter can be any combination (for the same DMA) of the following values:
|
||||
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
|
||||
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
|
||||
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
|
||||
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
|
||||
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
|
||||
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
|
||||
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
|
||||
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
|
||||
* @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
|
||||
* @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
|
||||
* @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
|
||||
* @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
|
||||
* @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_ClearFlag(uint32_t DMAy_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
|
||||
|
||||
/* Calculate the used DMAy */
|
||||
if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
|
||||
{
|
||||
/* Clear the selected DMAy flags */
|
||||
DMA2->IFCR = DMAy_FLAG;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the selected DMAy flags */
|
||||
DMA1->IFCR = DMAy_FLAG;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
|
||||
* @param DMAy_IT: specifies the DMAy interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
|
||||
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
|
||||
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
|
||||
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
|
||||
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
|
||||
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
|
||||
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
|
||||
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
|
||||
* @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
|
||||
* @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
|
||||
* @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
|
||||
* @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
|
||||
* @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
|
||||
* @retval The new state of DMAy_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_GET_IT(DMAy_IT));
|
||||
|
||||
/* Calculate the used DMA */
|
||||
if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
|
||||
{
|
||||
/* Get DMA2 ISR register value */
|
||||
tmpreg = DMA2->ISR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get DMA1 ISR register value */
|
||||
tmpreg = DMA1->ISR;
|
||||
}
|
||||
|
||||
/* Check the status of the specified DMAy interrupt */
|
||||
if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
|
||||
{
|
||||
/* DMAy_IT is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DMAy_IT is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the DMA_IT status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DMAy Channelx's interrupt pending bits.
|
||||
* @param DMAy_IT: specifies the DMAy interrupt pending bit to clear.
|
||||
* This parameter can be any combination (for the same DMA) of the following values:
|
||||
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
|
||||
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
|
||||
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
|
||||
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
|
||||
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
|
||||
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
|
||||
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
|
||||
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
|
||||
* @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
|
||||
* @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
|
||||
* @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
|
||||
* @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
|
||||
* @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_ClearITPendingBit(uint32_t DMAy_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
|
||||
|
||||
/* Calculate the used DMAy */
|
||||
if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
|
||||
{
|
||||
/* Clear the selected DMAy interrupt pending bits */
|
||||
DMA2->IFCR = DMAy_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the selected DMAy interrupt pending bits */
|
||||
DMA1->IFCR = DMAy_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,439 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_dma.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the DMA firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_DMA_H
|
||||
#define __STM32F10x_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DMA Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
|
||||
|
||||
uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
|
||||
|
||||
uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
|
||||
This parameter can be a value of @ref DMA_data_transfer_direction */
|
||||
|
||||
uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
|
||||
The data unit is equal to the configuration set in DMA_PeripheralDataSize
|
||||
or DMA_MemoryDataSize members depending in the transfer direction. */
|
||||
|
||||
uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
|
||||
|
||||
uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_memory_incremented_mode */
|
||||
|
||||
uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_peripheral_data_size */
|
||||
|
||||
uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_memory_data_size */
|
||||
|
||||
uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_circular_normal_mode.
|
||||
@note: The circular buffer mode cannot be used if the memory-to-memory
|
||||
data transfer is configured on the selected Channel */
|
||||
|
||||
uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_priority_level */
|
||||
|
||||
uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
|
||||
This parameter can be a value of @ref DMA_memory_to_memory */
|
||||
}DMA_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
|
||||
((PERIPH) == DMA1_Channel2) || \
|
||||
((PERIPH) == DMA1_Channel3) || \
|
||||
((PERIPH) == DMA1_Channel4) || \
|
||||
((PERIPH) == DMA1_Channel5) || \
|
||||
((PERIPH) == DMA1_Channel6) || \
|
||||
((PERIPH) == DMA1_Channel7) || \
|
||||
((PERIPH) == DMA2_Channel1) || \
|
||||
((PERIPH) == DMA2_Channel2) || \
|
||||
((PERIPH) == DMA2_Channel3) || \
|
||||
((PERIPH) == DMA2_Channel4) || \
|
||||
((PERIPH) == DMA2_Channel5))
|
||||
|
||||
/** @defgroup DMA_data_transfer_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
|
||||
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
|
||||
#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
|
||||
((DIR) == DMA_DIR_PeripheralSRC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_peripheral_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
|
||||
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
|
||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
|
||||
((STATE) == DMA_PeripheralInc_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_memory_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
|
||||
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
|
||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
|
||||
((STATE) == DMA_MemoryInc_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_peripheral_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
|
||||
#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
|
||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
|
||||
((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
|
||||
((SIZE) == DMA_PeripheralDataSize_Word))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_memory_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
|
||||
#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
|
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
|
||||
((SIZE) == DMA_MemoryDataSize_HalfWord) || \
|
||||
((SIZE) == DMA_MemoryDataSize_Word))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_circular_normal_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_Mode_Circular ((uint32_t)0x00000020)
|
||||
#define DMA_Mode_Normal ((uint32_t)0x00000000)
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_priority_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
|
||||
#define DMA_Priority_High ((uint32_t)0x00002000)
|
||||
#define DMA_Priority_Medium ((uint32_t)0x00001000)
|
||||
#define DMA_Priority_Low ((uint32_t)0x00000000)
|
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
|
||||
((PRIORITY) == DMA_Priority_High) || \
|
||||
((PRIORITY) == DMA_Priority_Medium) || \
|
||||
((PRIORITY) == DMA_Priority_Low))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_memory_to_memory
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_M2M_Enable ((uint32_t)0x00004000)
|
||||
#define DMA_M2M_Disable ((uint32_t)0x00000000)
|
||||
#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_IT_TC ((uint32_t)0x00000002)
|
||||
#define DMA_IT_HT ((uint32_t)0x00000004)
|
||||
#define DMA_IT_TE ((uint32_t)0x00000008)
|
||||
#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
#define DMA1_IT_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA1_IT_TC1 ((uint32_t)0x00000002)
|
||||
#define DMA1_IT_HT1 ((uint32_t)0x00000004)
|
||||
#define DMA1_IT_TE1 ((uint32_t)0x00000008)
|
||||
#define DMA1_IT_GL2 ((uint32_t)0x00000010)
|
||||
#define DMA1_IT_TC2 ((uint32_t)0x00000020)
|
||||
#define DMA1_IT_HT2 ((uint32_t)0x00000040)
|
||||
#define DMA1_IT_TE2 ((uint32_t)0x00000080)
|
||||
#define DMA1_IT_GL3 ((uint32_t)0x00000100)
|
||||
#define DMA1_IT_TC3 ((uint32_t)0x00000200)
|
||||
#define DMA1_IT_HT3 ((uint32_t)0x00000400)
|
||||
#define DMA1_IT_TE3 ((uint32_t)0x00000800)
|
||||
#define DMA1_IT_GL4 ((uint32_t)0x00001000)
|
||||
#define DMA1_IT_TC4 ((uint32_t)0x00002000)
|
||||
#define DMA1_IT_HT4 ((uint32_t)0x00004000)
|
||||
#define DMA1_IT_TE4 ((uint32_t)0x00008000)
|
||||
#define DMA1_IT_GL5 ((uint32_t)0x00010000)
|
||||
#define DMA1_IT_TC5 ((uint32_t)0x00020000)
|
||||
#define DMA1_IT_HT5 ((uint32_t)0x00040000)
|
||||
#define DMA1_IT_TE5 ((uint32_t)0x00080000)
|
||||
#define DMA1_IT_GL6 ((uint32_t)0x00100000)
|
||||
#define DMA1_IT_TC6 ((uint32_t)0x00200000)
|
||||
#define DMA1_IT_HT6 ((uint32_t)0x00400000)
|
||||
#define DMA1_IT_TE6 ((uint32_t)0x00800000)
|
||||
#define DMA1_IT_GL7 ((uint32_t)0x01000000)
|
||||
#define DMA1_IT_TC7 ((uint32_t)0x02000000)
|
||||
#define DMA1_IT_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA1_IT_TE7 ((uint32_t)0x08000000)
|
||||
|
||||
#define DMA2_IT_GL1 ((uint32_t)0x10000001)
|
||||
#define DMA2_IT_TC1 ((uint32_t)0x10000002)
|
||||
#define DMA2_IT_HT1 ((uint32_t)0x10000004)
|
||||
#define DMA2_IT_TE1 ((uint32_t)0x10000008)
|
||||
#define DMA2_IT_GL2 ((uint32_t)0x10000010)
|
||||
#define DMA2_IT_TC2 ((uint32_t)0x10000020)
|
||||
#define DMA2_IT_HT2 ((uint32_t)0x10000040)
|
||||
#define DMA2_IT_TE2 ((uint32_t)0x10000080)
|
||||
#define DMA2_IT_GL3 ((uint32_t)0x10000100)
|
||||
#define DMA2_IT_TC3 ((uint32_t)0x10000200)
|
||||
#define DMA2_IT_HT3 ((uint32_t)0x10000400)
|
||||
#define DMA2_IT_TE3 ((uint32_t)0x10000800)
|
||||
#define DMA2_IT_GL4 ((uint32_t)0x10001000)
|
||||
#define DMA2_IT_TC4 ((uint32_t)0x10002000)
|
||||
#define DMA2_IT_HT4 ((uint32_t)0x10004000)
|
||||
#define DMA2_IT_TE4 ((uint32_t)0x10008000)
|
||||
#define DMA2_IT_GL5 ((uint32_t)0x10010000)
|
||||
#define DMA2_IT_TC5 ((uint32_t)0x10020000)
|
||||
#define DMA2_IT_HT5 ((uint32_t)0x10040000)
|
||||
#define DMA2_IT_TE5 ((uint32_t)0x10080000)
|
||||
|
||||
#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
|
||||
|
||||
#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
|
||||
((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
|
||||
((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
|
||||
((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
|
||||
((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
|
||||
((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
|
||||
((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
|
||||
((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
|
||||
((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
|
||||
((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
|
||||
((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
|
||||
((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
|
||||
((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
|
||||
((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
|
||||
((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
|
||||
((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
|
||||
((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
|
||||
((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
|
||||
((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
|
||||
((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
|
||||
((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
|
||||
((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
|
||||
((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
|
||||
((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_flags_definition
|
||||
* @{
|
||||
*/
|
||||
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
|
||||
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
|
||||
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
|
||||
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
|
||||
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
|
||||
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
|
||||
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
|
||||
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
|
||||
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
|
||||
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
|
||||
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
|
||||
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
|
||||
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
|
||||
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
|
||||
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
|
||||
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
|
||||
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
|
||||
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
|
||||
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
|
||||
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
|
||||
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
|
||||
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
|
||||
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
|
||||
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
|
||||
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
|
||||
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
|
||||
|
||||
#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
|
||||
#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
|
||||
#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
|
||||
#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
|
||||
#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
|
||||
#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
|
||||
#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
|
||||
#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
|
||||
#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
|
||||
#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
|
||||
#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
|
||||
#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
|
||||
#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
|
||||
#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
|
||||
#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
|
||||
#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
|
||||
#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
|
||||
#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
|
||||
#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
|
||||
#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
|
||||
|
||||
#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
|
||||
|
||||
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
|
||||
((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
|
||||
((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
|
||||
((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
|
||||
((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
|
||||
((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
|
||||
((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
|
||||
((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
|
||||
((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
|
||||
((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
|
||||
((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
|
||||
((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
|
||||
((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
|
||||
((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
|
||||
((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
|
||||
((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
|
||||
((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
|
||||
((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
|
||||
((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
|
||||
((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
|
||||
((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
|
||||
((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
|
||||
((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
|
||||
((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Buffer_Size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
|
||||
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
|
||||
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
|
||||
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
|
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
|
||||
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
|
||||
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
|
||||
void DMA_ClearFlag(uint32_t DMAy_FLAG);
|
||||
ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
|
||||
void DMA_ClearITPendingBit(uint32_t DMAy_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F10x_DMA_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,269 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_exti.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the EXTI firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_exti.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI
|
||||
* @brief EXTI driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the EXTI peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_DeInit(void)
|
||||
{
|
||||
EXTI->IMR = 0x00000000;
|
||||
EXTI->EMR = 0x00000000;
|
||||
EXTI->RTSR = 0x00000000;
|
||||
EXTI->FTSR = 0x00000000;
|
||||
EXTI->PR = 0x000FFFFF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the EXTI peripheral according to the specified
|
||||
* parameters in the EXTI_InitStruct.
|
||||
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
|
||||
* that contains the configuration information for the EXTI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
|
||||
assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
|
||||
assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
|
||||
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
|
||||
|
||||
tmp = (uint32_t)EXTI_BASE;
|
||||
|
||||
if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
|
||||
{
|
||||
/* Clear EXTI line configuration */
|
||||
EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
|
||||
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||
|
||||
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
|
||||
/* Select the trigger for the selected external interrupts */
|
||||
if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
|
||||
{
|
||||
/* Rising Falling edge */
|
||||
EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp = (uint32_t)EXTI_BASE;
|
||||
tmp += EXTI_InitStruct->EXTI_Trigger;
|
||||
|
||||
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||
|
||||
/* Disable the selected external lines */
|
||||
*(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each EXTI_InitStruct member with its reset value.
|
||||
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
|
||||
{
|
||||
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
|
||||
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
|
||||
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
|
||||
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generates a Software interrupt.
|
||||
* @param EXTI_Line: specifies the EXTI lines to be enabled or disabled.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..19).
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||
|
||||
EXTI->SWIER |= EXTI_Line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line flag is set or not.
|
||||
* @param EXTI_Line: specifies the EXTI line flag to check.
|
||||
* This parameter can be:
|
||||
* @arg EXTI_Linex: External interrupt line x where x(0..19)
|
||||
* @retval The new state of EXTI_Line (SET or RESET).
|
||||
*/
|
||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
|
||||
|
||||
if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending flags.
|
||||
* @param EXTI_Line: specifies the EXTI lines flags to clear.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..19).
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_ClearFlag(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||
|
||||
EXTI->PR = EXTI_Line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line is asserted or not.
|
||||
* @param EXTI_Line: specifies the EXTI line to check.
|
||||
* This parameter can be:
|
||||
* @arg EXTI_Linex: External interrupt line x where x(0..19)
|
||||
* @retval The new state of EXTI_Line (SET or RESET).
|
||||
*/
|
||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t enablestatus = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
|
||||
|
||||
enablestatus = EXTI->IMR & EXTI_Line;
|
||||
if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending bits.
|
||||
* @param EXTI_Line: specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..19).
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||
|
||||
EXTI->PR = EXTI_Line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,184 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_exti.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the EXTI firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_EXTI_H
|
||||
#define __STM32F10x_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief EXTI mode enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Mode_Interrupt = 0x00,
|
||||
EXTI_Mode_Event = 0x04
|
||||
}EXTIMode_TypeDef;
|
||||
|
||||
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
|
||||
|
||||
/**
|
||||
* @brief EXTI Trigger enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Trigger_Rising = 0x08,
|
||||
EXTI_Trigger_Falling = 0x0C,
|
||||
EXTI_Trigger_Rising_Falling = 0x10
|
||||
}EXTITrigger_TypeDef;
|
||||
|
||||
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
|
||||
((TRIGGER) == EXTI_Trigger_Falling) || \
|
||||
((TRIGGER) == EXTI_Trigger_Rising_Falling))
|
||||
/**
|
||||
* @brief EXTI Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
|
||||
This parameter can be any combination of @ref EXTI_Lines */
|
||||
|
||||
EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTIMode_TypeDef */
|
||||
|
||||
EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTIMode_TypeDef */
|
||||
|
||||
FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
}EXTI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Lines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
|
||||
#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
|
||||
#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
|
||||
#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
|
||||
#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
|
||||
#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
|
||||
#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
|
||||
#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
|
||||
#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
|
||||
#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
|
||||
#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
|
||||
#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
|
||||
#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
|
||||
#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
|
||||
#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
|
||||
#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
|
||||
#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
|
||||
#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
|
||||
#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS
|
||||
Wakeup from suspend event */
|
||||
#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
|
||||
|
||||
#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
|
||||
#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
|
||||
((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
|
||||
((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
|
||||
((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
|
||||
((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
|
||||
((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
|
||||
((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
|
||||
((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
|
||||
((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
|
||||
((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void EXTI_DeInit(void);
|
||||
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
|
||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClearFlag(uint32_t EXTI_Line);
|
||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_EXTI_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,426 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_flash.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the FLASH
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_FLASH_H
|
||||
#define __STM32F10x_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Status
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
FLASH_BUSY = 1,
|
||||
FLASH_ERROR_PG,
|
||||
FLASH_ERROR_WRP,
|
||||
FLASH_COMPLETE,
|
||||
FLASH_TIMEOUT
|
||||
}FLASH_Status;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup Flash_Latency
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
|
||||
#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */
|
||||
#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */
|
||||
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
|
||||
((LATENCY) == FLASH_Latency_1) || \
|
||||
((LATENCY) == FLASH_Latency_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Half_Cycle_Enable_Disable
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */
|
||||
#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */
|
||||
#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \
|
||||
((STATE) == FLASH_HalfCycleAccess_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Prefetch_Buffer_Enable_Disable
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */
|
||||
#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */
|
||||
#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \
|
||||
((STATE) == FLASH_PrefetchBuffer_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_Write_Protection
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Values to be used with STM32 Low and Medium density devices */
|
||||
#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */
|
||||
#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */
|
||||
#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */
|
||||
#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */
|
||||
#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */
|
||||
#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */
|
||||
#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */
|
||||
#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */
|
||||
|
||||
/* Values to be used with STM32 Medium-density devices */
|
||||
#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */
|
||||
#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */
|
||||
#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */
|
||||
#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */
|
||||
#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */
|
||||
#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */
|
||||
#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */
|
||||
#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */
|
||||
#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */
|
||||
#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */
|
||||
#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */
|
||||
#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */
|
||||
#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */
|
||||
#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */
|
||||
#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */
|
||||
#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */
|
||||
#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */
|
||||
#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */
|
||||
#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */
|
||||
#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */
|
||||
#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */
|
||||
#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */
|
||||
#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */
|
||||
#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */
|
||||
|
||||
/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */
|
||||
#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 0 to 1 */
|
||||
#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 2 to 3 */
|
||||
#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 4 to 5 */
|
||||
#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 6 to 7 */
|
||||
#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 8 to 9 */
|
||||
#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 10 to 11 */
|
||||
#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 12 to 13 */
|
||||
#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 14 to 15 */
|
||||
#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 16 to 17 */
|
||||
#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 18 to 19 */
|
||||
#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 20 to 21 */
|
||||
#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 22 to 23 */
|
||||
#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 24 to 25 */
|
||||
#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 26 to 27 */
|
||||
#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 28 to 29 */
|
||||
#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 30 to 31 */
|
||||
#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 32 to 33 */
|
||||
#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 34 to 35 */
|
||||
#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 36 to 37 */
|
||||
#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 38 to 39 */
|
||||
#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 40 to 41 */
|
||||
#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 42 to 43 */
|
||||
#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 44 to 45 */
|
||||
#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 46 to 47 */
|
||||
#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 48 to 49 */
|
||||
#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 50 to 51 */
|
||||
#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 52 to 53 */
|
||||
#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 54 to 55 */
|
||||
#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 56 to 57 */
|
||||
#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 58 to 59 */
|
||||
#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||
Write protection of page 60 to 61 */
|
||||
#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */
|
||||
#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */
|
||||
#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */
|
||||
|
||||
#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
|
||||
|
||||
#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
|
||||
|
||||
#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF))
|
||||
|
||||
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_IWatchdog
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */
|
||||
#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */
|
||||
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_nRST_STOP
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
|
||||
#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
|
||||
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_nRST_STDBY
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
|
||||
#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
|
||||
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
|
||||
|
||||
#ifdef STM32F10X_XL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup FLASH_Boot
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position
|
||||
and this parameter is selected the device will boot from Bank1(Default) */
|
||||
#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position
|
||||
and this parameter is selected the device will boot from Bank 2 or Bank 1,
|
||||
depending on the activation of the bank */
|
||||
#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2))
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup FLASH_Interrupts
|
||||
* @{
|
||||
*/
|
||||
#ifdef STM32F10X_XL
|
||||
#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */
|
||||
#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */
|
||||
|
||||
#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */
|
||||
#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */
|
||||
|
||||
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */
|
||||
#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */
|
||||
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
|
||||
#else
|
||||
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */
|
||||
#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */
|
||||
#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */
|
||||
#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */
|
||||
|
||||
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Flags
|
||||
* @{
|
||||
*/
|
||||
#ifdef STM32F10X_XL
|
||||
#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */
|
||||
#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */
|
||||
#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */
|
||||
#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */
|
||||
|
||||
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/
|
||||
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */
|
||||
#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */
|
||||
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */
|
||||
|
||||
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
|
||||
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
|
||||
#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
|
||||
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
|
||||
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
|
||||
|
||||
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
|
||||
((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
|
||||
((FLAG) == FLASH_FLAG_OPTERR)|| \
|
||||
((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
|
||||
((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
|
||||
((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \
|
||||
((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR))
|
||||
#else
|
||||
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
|
||||
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
|
||||
#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
|
||||
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
|
||||
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
|
||||
|
||||
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/
|
||||
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */
|
||||
#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */
|
||||
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */
|
||||
|
||||
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
|
||||
((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
|
||||
((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
|
||||
((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
|
||||
((FLAG) == FLASH_FLAG_OPTERR))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*------------ Functions used for all STM32F10x devices -----*/
|
||||
void FLASH_SetLatency(uint32_t FLASH_Latency);
|
||||
void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
|
||||
void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
|
||||
void FLASH_Unlock(void);
|
||||
void FLASH_Lock(void);
|
||||
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
|
||||
FLASH_Status FLASH_EraseAllPages(void);
|
||||
FLASH_Status FLASH_EraseOptionBytes(void);
|
||||
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
|
||||
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
|
||||
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
|
||||
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
|
||||
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
|
||||
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
|
||||
uint32_t FLASH_GetUserOptionByte(void);
|
||||
uint32_t FLASH_GetWriteProtectionOptionByte(void);
|
||||
FlagStatus FLASH_GetReadOutProtectionStatus(void);
|
||||
FlagStatus FLASH_GetPrefetchBufferStatus(void);
|
||||
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
|
||||
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
|
||||
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
|
||||
FLASH_Status FLASH_GetStatus(void);
|
||||
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
|
||||
/*------------ New function used for all STM32F10x devices -----*/
|
||||
void FLASH_UnlockBank1(void);
|
||||
void FLASH_LockBank1(void);
|
||||
FLASH_Status FLASH_EraseAllBank1Pages(void);
|
||||
FLASH_Status FLASH_GetBank1Status(void);
|
||||
FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
|
||||
|
||||
#ifdef STM32F10X_XL
|
||||
/*---- New Functions used only with STM32F10x_XL density devices -----*/
|
||||
void FLASH_UnlockBank2(void);
|
||||
void FLASH_LockBank2(void);
|
||||
FLASH_Status FLASH_EraseAllBank2Pages(void);
|
||||
FLASH_Status FLASH_GetBank2Status(void);
|
||||
FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout);
|
||||
FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT);
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_FLASH_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,866 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_fsmc.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the FSMC firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_fsmc.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC
|
||||
* @brief FSMC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* --------------------- FSMC registers bit mask ---------------------------- */
|
||||
|
||||
/* FSMC BCRx Mask */
|
||||
#define BCR_MBKEN_Set ((uint32_t)0x00000001)
|
||||
#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)
|
||||
#define BCR_FACCEN_Set ((uint32_t)0x00000040)
|
||||
|
||||
/* FSMC PCRx Mask */
|
||||
#define PCR_PBKEN_Set ((uint32_t)0x00000004)
|
||||
#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)
|
||||
#define PCR_ECCEN_Set ((uint32_t)0x00000040)
|
||||
#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)
|
||||
#define PCR_MemoryType_NAND ((uint32_t)0x00000008)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
|
||||
* reset values.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
|
||||
* @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
|
||||
* @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
|
||||
* @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
|
||||
|
||||
/* FSMC_Bank1_NORSRAM1 */
|
||||
if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
|
||||
{
|
||||
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
|
||||
}
|
||||
/* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
|
||||
else
|
||||
{
|
||||
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
|
||||
}
|
||||
FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
|
||||
FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the FSMC NAND Banks registers to their default reset values.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NANDDeInit(uint32_t FSMC_Bank)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
|
||||
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
/* Set the FSMC_Bank2 registers to their reset values */
|
||||
FSMC_Bank2->PCR2 = 0x00000018;
|
||||
FSMC_Bank2->SR2 = 0x00000040;
|
||||
FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
|
||||
FSMC_Bank2->PATT2 = 0xFCFCFCFC;
|
||||
}
|
||||
/* FSMC_Bank3_NAND */
|
||||
else
|
||||
{
|
||||
/* Set the FSMC_Bank3 registers to their reset values */
|
||||
FSMC_Bank3->PCR3 = 0x00000018;
|
||||
FSMC_Bank3->SR3 = 0x00000040;
|
||||
FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
|
||||
FSMC_Bank3->PATT3 = 0xFCFCFCFC;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_PCCARDDeInit(void)
|
||||
{
|
||||
/* Set the FSMC_Bank4 registers to their reset values */
|
||||
FSMC_Bank4->PCR4 = 0x00000018;
|
||||
FSMC_Bank4->SR4 = 0x00000000;
|
||||
FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
|
||||
FSMC_Bank4->PATT4 = 0xFCFCFCFC;
|
||||
FSMC_Bank4->PIO4 = 0xFCFCFCFC;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the FSMC NOR/SRAM Banks according to the specified
|
||||
* parameters in the FSMC_NORSRAMInitStruct.
|
||||
* @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
|
||||
* structure that contains the configuration information for
|
||||
* the FSMC NOR/SRAM specified Banks.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
|
||||
assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
|
||||
assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
|
||||
assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
|
||||
assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
|
||||
assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
|
||||
assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
|
||||
assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
|
||||
assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
|
||||
assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
|
||||
assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
|
||||
assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
|
||||
assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
|
||||
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
|
||||
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
|
||||
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
|
||||
assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
|
||||
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
|
||||
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
|
||||
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
|
||||
|
||||
/* Bank1 NOR/SRAM control register configuration */
|
||||
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
|
||||
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
|
||||
FSMC_NORSRAMInitStruct->FSMC_MemoryType |
|
||||
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
|
||||
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
|
||||
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WrapMode |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
|
||||
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
|
||||
|
||||
if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
|
||||
{
|
||||
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
|
||||
}
|
||||
|
||||
/* Bank1 NOR/SRAM timing register configuration */
|
||||
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
|
||||
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
|
||||
|
||||
|
||||
/* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
|
||||
if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
|
||||
{
|
||||
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
|
||||
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
|
||||
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
|
||||
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
|
||||
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
|
||||
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
|
||||
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
|
||||
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
|
||||
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
|
||||
}
|
||||
else
|
||||
{
|
||||
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the FSMC NAND Banks according to the specified
|
||||
* parameters in the FSMC_NANDInitStruct.
|
||||
* @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef
|
||||
* structure that contains the configuration information for the FSMC
|
||||
* NAND specified Banks.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
|
||||
{
|
||||
uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
|
||||
assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
|
||||
assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
|
||||
assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
|
||||
assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
|
||||
assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
|
||||
assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
|
||||
assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
|
||||
assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
|
||||
assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
|
||||
assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
|
||||
assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
|
||||
assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
|
||||
assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
|
||||
assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
|
||||
|
||||
/* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
|
||||
tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
|
||||
PCR_MemoryType_NAND |
|
||||
FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
|
||||
FSMC_NANDInitStruct->FSMC_ECC |
|
||||
FSMC_NANDInitStruct->FSMC_ECCPageSize |
|
||||
(FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
|
||||
(FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
|
||||
|
||||
/* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
|
||||
tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
|
||||
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||||
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
||||
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||||
|
||||
/* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
|
||||
tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
|
||||
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||||
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
||||
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||||
|
||||
if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
/* FSMC_Bank2_NAND registers configuration */
|
||||
FSMC_Bank2->PCR2 = tmppcr;
|
||||
FSMC_Bank2->PMEM2 = tmppmem;
|
||||
FSMC_Bank2->PATT2 = tmppatt;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* FSMC_Bank3_NAND registers configuration */
|
||||
FSMC_Bank3->PCR3 = tmppcr;
|
||||
FSMC_Bank3->PMEM3 = tmppmem;
|
||||
FSMC_Bank3->PATT3 = tmppatt;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the FSMC PCCARD Bank according to the specified
|
||||
* parameters in the FSMC_PCCARDInitStruct.
|
||||
* @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
|
||||
* structure that contains the configuration information for the FSMC
|
||||
* PCCARD Bank.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
|
||||
assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
|
||||
assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
|
||||
|
||||
assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
|
||||
assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
|
||||
assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
|
||||
assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
|
||||
|
||||
assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
|
||||
assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
|
||||
assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
|
||||
assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
|
||||
assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
|
||||
assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
|
||||
assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
|
||||
assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
|
||||
|
||||
/* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
|
||||
FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
|
||||
FSMC_MemoryDataWidth_16b |
|
||||
(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
|
||||
(FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
|
||||
|
||||
/* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
|
||||
FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
|
||||
(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||||
(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
||||
(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||||
|
||||
/* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
|
||||
FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
|
||||
(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||||
(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
||||
(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||||
|
||||
/* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
|
||||
FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
|
||||
(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||||
(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
||||
(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
|
||||
* @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
|
||||
* structure which will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
|
||||
{
|
||||
/* Reset NOR/SRAM Init structure parameters values */
|
||||
FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
|
||||
FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
|
||||
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
|
||||
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each FSMC_NANDInitStruct member with its default value.
|
||||
* @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef
|
||||
* structure which will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
|
||||
{
|
||||
/* Reset NAND Init structure parameters values */
|
||||
FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
|
||||
FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
|
||||
FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
|
||||
FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
|
||||
FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
|
||||
FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
|
||||
FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
|
||||
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||||
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||||
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||||
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||||
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||||
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||||
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||||
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each FSMC_PCCARDInitStruct member with its default value.
|
||||
* @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef
|
||||
* structure which will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
|
||||
{
|
||||
/* Reset PCCARD Init structure parameters values */
|
||||
FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
|
||||
FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
|
||||
FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
|
||||
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||||
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified NOR/SRAM Memory Bank.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
|
||||
* @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
|
||||
* @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
|
||||
* @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
|
||||
* @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
|
||||
{
|
||||
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
|
||||
FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
|
||||
FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified NAND Memory Bank.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
|
||||
{
|
||||
assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
|
||||
}
|
||||
else
|
||||
{
|
||||
FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the PCCARD Memory Bank.
|
||||
* @param NewState: new state of the PCCARD Memory Bank.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_PCCARDCmd(FunctionalState NewState)
|
||||
{
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
|
||||
FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
|
||||
FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the FSMC NAND ECC feature.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @param NewState: new state of the FSMC NAND ECC feature.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
|
||||
{
|
||||
assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
|
||||
}
|
||||
else
|
||||
{
|
||||
FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the error correction code register value.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @retval The Error Correction Code (ECC) value.
|
||||
*/
|
||||
uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
|
||||
{
|
||||
uint32_t eccval = 0x00000000;
|
||||
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
/* Get the ECCR2 register value */
|
||||
eccval = FSMC_Bank2->ECCR2;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get the ECCR3 register value */
|
||||
eccval = FSMC_Bank3->ECCR3;
|
||||
}
|
||||
/* Return the error correction code value */
|
||||
return(eccval);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified FSMC interrupts.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
||||
* @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
|
||||
* @arg FSMC_IT_Level: Level edge detection interrupt.
|
||||
* @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
|
||||
* @param NewState: new state of the specified FSMC interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
|
||||
{
|
||||
assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
|
||||
assert_param(IS_FSMC_IT(FSMC_IT));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected FSMC_Bank2 interrupts */
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
FSMC_Bank2->SR2 |= FSMC_IT;
|
||||
}
|
||||
/* Enable the selected FSMC_Bank3 interrupts */
|
||||
else if (FSMC_Bank == FSMC_Bank3_NAND)
|
||||
{
|
||||
FSMC_Bank3->SR3 |= FSMC_IT;
|
||||
}
|
||||
/* Enable the selected FSMC_Bank4 interrupts */
|
||||
else
|
||||
{
|
||||
FSMC_Bank4->SR4 |= FSMC_IT;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected FSMC_Bank2 interrupts */
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
|
||||
FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
|
||||
}
|
||||
/* Disable the selected FSMC_Bank3 interrupts */
|
||||
else if (FSMC_Bank == FSMC_Bank3_NAND)
|
||||
{
|
||||
FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
|
||||
}
|
||||
/* Disable the selected FSMC_Bank4 interrupts */
|
||||
else
|
||||
{
|
||||
FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified FSMC flag is set or not.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
||||
* @param FSMC_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
|
||||
* @arg FSMC_FLAG_Level: Level detection Flag.
|
||||
* @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
|
||||
* @arg FSMC_FLAG_FEMPT: Fifo empty Flag.
|
||||
* @retval The new state of FSMC_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
uint32_t tmpsr = 0x00000000;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
|
||||
assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
|
||||
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
tmpsr = FSMC_Bank2->SR2;
|
||||
}
|
||||
else if(FSMC_Bank == FSMC_Bank3_NAND)
|
||||
{
|
||||
tmpsr = FSMC_Bank3->SR3;
|
||||
}
|
||||
/* FSMC_Bank4_PCCARD*/
|
||||
else
|
||||
{
|
||||
tmpsr = FSMC_Bank4->SR4;
|
||||
}
|
||||
|
||||
/* Get the flag status */
|
||||
if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the flag status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the FSMC's pending flags.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
||||
* @param FSMC_FLAG: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
|
||||
* @arg FSMC_FLAG_Level: Level detection Flag.
|
||||
* @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
|
||||
assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
|
||||
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
FSMC_Bank2->SR2 &= ~FSMC_FLAG;
|
||||
}
|
||||
else if(FSMC_Bank == FSMC_Bank3_NAND)
|
||||
{
|
||||
FSMC_Bank3->SR3 &= ~FSMC_FLAG;
|
||||
}
|
||||
/* FSMC_Bank4_PCCARD*/
|
||||
else
|
||||
{
|
||||
FSMC_Bank4->SR4 &= ~FSMC_FLAG;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified FSMC interrupt has occurred or not.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
||||
* @param FSMC_IT: specifies the FSMC interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
|
||||
* @arg FSMC_IT_Level: Level edge detection interrupt.
|
||||
* @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
|
||||
* @retval The new state of FSMC_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
|
||||
assert_param(IS_FSMC_GET_IT(FSMC_IT));
|
||||
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
tmpsr = FSMC_Bank2->SR2;
|
||||
}
|
||||
else if(FSMC_Bank == FSMC_Bank3_NAND)
|
||||
{
|
||||
tmpsr = FSMC_Bank3->SR3;
|
||||
}
|
||||
/* FSMC_Bank4_PCCARD*/
|
||||
else
|
||||
{
|
||||
tmpsr = FSMC_Bank4->SR4;
|
||||
}
|
||||
|
||||
itstatus = tmpsr & FSMC_IT;
|
||||
|
||||
itenable = tmpsr & (FSMC_IT >> 3);
|
||||
if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the FSMC's interrupt pending bits.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
||||
* @param FSMC_IT: specifies the interrupt pending bit to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
|
||||
* @arg FSMC_IT_Level: Level edge detection interrupt.
|
||||
* @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
|
||||
assert_param(IS_FSMC_IT(FSMC_IT));
|
||||
|
||||
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||
{
|
||||
FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
|
||||
}
|
||||
else if(FSMC_Bank == FSMC_Bank3_NAND)
|
||||
{
|
||||
FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
|
||||
}
|
||||
/* FSMC_Bank4_PCCARD*/
|
||||
else
|
||||
{
|
||||
FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,733 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_fsmc.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the FSMC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_FSMC_H
|
||||
#define __STM32F10x_FSMC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FSMC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Timing parameters For NOR/SRAM Banks
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the address setup time.
|
||||
This parameter can be a value between 0 and 0xF.
|
||||
@note: It is not used with synchronous NOR Flash memories. */
|
||||
|
||||
uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the address hold time.
|
||||
This parameter can be a value between 0 and 0xF.
|
||||
@note: It is not used with synchronous NOR Flash memories.*/
|
||||
|
||||
uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the data setup time.
|
||||
This parameter can be a value between 0 and 0xFF.
|
||||
@note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
|
||||
|
||||
uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the bus turnaround.
|
||||
This parameter can be a value between 0 and 0xF.
|
||||
@note: It is only used for multiplexed NOR Flash memories. */
|
||||
|
||||
uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
|
||||
This parameter can be a value between 1 and 0xF.
|
||||
@note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
|
||||
|
||||
uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
|
||||
to the memory before getting the first data.
|
||||
The value of this parameter depends on the memory type as shown below:
|
||||
- It must be set to 0 in case of a CRAM
|
||||
- It is don't care in asynchronous NOR, SRAM or ROM accesses
|
||||
- It may assume a value between 0 and 0xF in NOR Flash memories
|
||||
with synchronous burst mode enable */
|
||||
|
||||
uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
|
||||
This parameter can be a value of @ref FSMC_Access_Mode */
|
||||
}FSMC_NORSRAMTimingInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FSMC NOR/SRAM Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
|
||||
This parameter can be a value of @ref FSMC_NORSRAM_Bank */
|
||||
|
||||
uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
|
||||
multiplexed on the databus or not.
|
||||
This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
|
||||
|
||||
uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
|
||||
the corresponding memory bank.
|
||||
This parameter can be a value of @ref FSMC_Memory_Type */
|
||||
|
||||
uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
|
||||
This parameter can be a value of @ref FSMC_Data_Width */
|
||||
|
||||
uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
|
||||
valid only with synchronous burst Flash memories.
|
||||
This parameter can be a value of @ref FSMC_Burst_Access_Mode */
|
||||
|
||||
uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
|
||||
valid only with asynchronous Flash memories.
|
||||
This parameter can be a value of @ref FSMC_AsynchronousWait */
|
||||
|
||||
uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
|
||||
the Flash memory in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
|
||||
|
||||
uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
|
||||
memory, valid only when accessing Flash memories in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wrap_Mode */
|
||||
|
||||
uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
|
||||
clock cycle before the wait state or during the wait state,
|
||||
valid only when accessing memories in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wait_Timing */
|
||||
|
||||
uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
|
||||
This parameter can be a value of @ref FSMC_Write_Operation */
|
||||
|
||||
uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
|
||||
signal, valid for Flash memory access in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wait_Signal */
|
||||
|
||||
uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
|
||||
This parameter can be a value of @ref FSMC_Extended_Mode */
|
||||
|
||||
uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
|
||||
This parameter can be a value of @ref FSMC_Write_Burst */
|
||||
|
||||
FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
|
||||
|
||||
FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
|
||||
}FSMC_NORSRAMInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief Timing parameters For FSMC NAND and PCCARD Banks
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
|
||||
the command assertion for NAND-Flash read or write access
|
||||
to common/Attribute or I/O memory space (depending on
|
||||
the memory space timing to be configured).
|
||||
This parameter can be a value between 0 and 0xFF.*/
|
||||
|
||||
uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
|
||||
command for NAND-Flash read or write access to
|
||||
common/Attribute or I/O memory space (depending on the
|
||||
memory space timing to be configured).
|
||||
This parameter can be a number between 0x00 and 0xFF */
|
||||
|
||||
uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
|
||||
(and data for write access) after the command deassertion
|
||||
for NAND-Flash read or write access to common/Attribute
|
||||
or I/O memory space (depending on the memory space timing
|
||||
to be configured).
|
||||
This parameter can be a number between 0x00 and 0xFF */
|
||||
|
||||
uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
|
||||
databus is kept in HiZ after the start of a NAND-Flash
|
||||
write access to common/Attribute or I/O memory space (depending
|
||||
on the memory space timing to be configured).
|
||||
This parameter can be a number between 0x00 and 0xFF */
|
||||
}FSMC_NAND_PCCARDTimingInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FSMC NAND Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.
|
||||
This parameter can be a value of @ref FSMC_NAND_Bank */
|
||||
|
||||
uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
|
||||
This parameter can be any value of @ref FSMC_Wait_feature */
|
||||
|
||||
uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
|
||||
This parameter can be any value of @ref FSMC_Data_Width */
|
||||
|
||||
uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.
|
||||
This parameter can be any value of @ref FSMC_ECC */
|
||||
|
||||
uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
|
||||
This parameter can be any value of @ref FSMC_ECC_Page_Size */
|
||||
|
||||
uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between CLE low and RE low.
|
||||
This parameter can be a value between 0 and 0xFF. */
|
||||
|
||||
uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between ALE low and RE low.
|
||||
This parameter can be a number between 0x0 and 0xFF */
|
||||
|
||||
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
|
||||
|
||||
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
|
||||
}FSMC_NANDInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FSMC PCCARD Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
|
||||
This parameter can be any value of @ref FSMC_Wait_feature */
|
||||
|
||||
uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between CLE low and RE low.
|
||||
This parameter can be a value between 0 and 0xFF. */
|
||||
|
||||
uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between ALE low and RE low.
|
||||
This parameter can be a number between 0x0 and 0xFF */
|
||||
|
||||
|
||||
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
|
||||
|
||||
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
|
||||
|
||||
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
|
||||
}FSMC_PCCARDInitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_NORSRAM_Bank
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
|
||||
#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
|
||||
#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
|
||||
#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_NAND_Bank
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_Bank2_NAND ((uint32_t)0x00000010)
|
||||
#define FSMC_Bank3_NAND ((uint32_t)0x00000100)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_PCCARD_Bank
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
|
||||
((BANK) == FSMC_Bank1_NORSRAM2) || \
|
||||
((BANK) == FSMC_Bank1_NORSRAM3) || \
|
||||
((BANK) == FSMC_Bank1_NORSRAM4))
|
||||
|
||||
#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
|
||||
((BANK) == FSMC_Bank3_NAND))
|
||||
|
||||
#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
|
||||
((BANK) == FSMC_Bank3_NAND) || \
|
||||
((BANK) == FSMC_Bank4_PCCARD))
|
||||
|
||||
#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
|
||||
((BANK) == FSMC_Bank3_NAND) || \
|
||||
((BANK) == FSMC_Bank4_PCCARD))
|
||||
|
||||
/** @defgroup NOR_SRAM_Controller
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Data_Address_Bus_Multiplexing
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
|
||||
#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
|
||||
((MUX) == FSMC_DataAddressMux_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Memory_Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
|
||||
#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
|
||||
#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
|
||||
#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
|
||||
((MEMORY) == FSMC_MemoryType_PSRAM)|| \
|
||||
((MEMORY) == FSMC_MemoryType_NOR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Data_Width
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
|
||||
#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
|
||||
#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
|
||||
((WIDTH) == FSMC_MemoryDataWidth_16b))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Burst_Access_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
|
||||
#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
|
||||
((STATE) == FSMC_BurstAccessMode_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_AsynchronousWait
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
|
||||
#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
|
||||
((STATE) == FSMC_AsynchronousWait_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_Signal_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
|
||||
#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
|
||||
#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
|
||||
((POLARITY) == FSMC_WaitSignalPolarity_High))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wrap_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
|
||||
#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
|
||||
((MODE) == FSMC_WrapMode_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_Timing
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
|
||||
#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
|
||||
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
|
||||
((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Write_Operation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
|
||||
#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
|
||||
((OPERATION) == FSMC_WriteOperation_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_Signal
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
|
||||
#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
|
||||
((SIGNAL) == FSMC_WaitSignal_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Extended_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
|
||||
|
||||
#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
|
||||
((MODE) == FSMC_ExtendedMode_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Write_Burst
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
|
||||
#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
|
||||
((BURST) == FSMC_WriteBurst_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Address_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Address_Hold_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Data_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Bus_Turn_around_Duration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_CLK_Division
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Data_Latency
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Access_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_AccessMode_A ((uint32_t)0x00000000)
|
||||
#define FSMC_AccessMode_B ((uint32_t)0x10000000)
|
||||
#define FSMC_AccessMode_C ((uint32_t)0x20000000)
|
||||
#define FSMC_AccessMode_D ((uint32_t)0x30000000)
|
||||
#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
|
||||
((MODE) == FSMC_AccessMode_B) || \
|
||||
((MODE) == FSMC_AccessMode_C) || \
|
||||
((MODE) == FSMC_AccessMode_D))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup NAND_PCCARD_Controller
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_feature
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
|
||||
#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
|
||||
((FEATURE) == FSMC_Waitfeature_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup FSMC_ECC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_ECC_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_ECC_Enable ((uint32_t)0x00000040)
|
||||
#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
|
||||
((STATE) == FSMC_ECC_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_ECC_Page_Size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
|
||||
#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
|
||||
#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
|
||||
#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
|
||||
#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
|
||||
#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
|
||||
#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
|
||||
((SIZE) == FSMC_ECCPageSize_512Bytes) || \
|
||||
((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
|
||||
((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
|
||||
((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
|
||||
((SIZE) == FSMC_ECCPageSize_8192Bytes))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_TCLR_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_TAR_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Hold_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_HiZ_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Interrupt_sources
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
|
||||
#define FSMC_IT_Level ((uint32_t)0x00000010)
|
||||
#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
|
||||
#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
|
||||
#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
|
||||
((IT) == FSMC_IT_Level) || \
|
||||
((IT) == FSMC_IT_FallingEdge))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
|
||||
#define FSMC_FLAG_Level ((uint32_t)0x00000002)
|
||||
#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
|
||||
#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
|
||||
#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
|
||||
((FLAG) == FSMC_FLAG_Level) || \
|
||||
((FLAG) == FSMC_FLAG_FallingEdge) || \
|
||||
((FLAG) == FSMC_FLAG_FEMPT))
|
||||
|
||||
#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
|
||||
void FSMC_NANDDeInit(uint32_t FSMC_Bank);
|
||||
void FSMC_PCCARDDeInit(void);
|
||||
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
|
||||
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
|
||||
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
|
||||
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
|
||||
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
|
||||
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
|
||||
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
|
||||
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
|
||||
void FSMC_PCCARDCmd(FunctionalState NewState);
|
||||
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
|
||||
uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
|
||||
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
|
||||
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
|
||||
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
|
||||
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
|
||||
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F10x_FSMC_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,650 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the GPIO firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_gpio.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO
|
||||
* @brief GPIO driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ------------ RCC registers bit address in the alias region ----------------*/
|
||||
#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
|
||||
|
||||
/* --- EVENTCR Register -----*/
|
||||
|
||||
/* Alias word address of EVOE bit */
|
||||
#define EVCR_OFFSET (AFIO_OFFSET + 0x00)
|
||||
#define EVOE_BitNumber ((uint8_t)0x07)
|
||||
#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
|
||||
|
||||
|
||||
/* --- MAPR Register ---*/
|
||||
/* Alias word address of MII_RMII_SEL bit */
|
||||
#define MAPR_OFFSET (AFIO_OFFSET + 0x04)
|
||||
#define MII_RMII_SEL_BitNumber ((u8)0x17)
|
||||
#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
|
||||
|
||||
|
||||
#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)
|
||||
#define LSB_MASK ((uint16_t)0xFFFF)
|
||||
#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
|
||||
#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
|
||||
#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
|
||||
#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the GPIOx peripheral registers to their default reset values.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
if (GPIOx == GPIOA)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOB)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOC)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOD)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOE)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOF)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (GPIOx == GPIOG)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the Alternate Functions (remap, event control
|
||||
* and EXTI configuration) registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_AFIODeInit(void)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the GPIOx peripheral according to the specified
|
||||
* parameters in the GPIO_InitStruct.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
|
||||
* contains the configuration information for the specified GPIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
|
||||
{
|
||||
uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
|
||||
uint32_t tmpreg = 0x00, pinmask = 0x00;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
|
||||
assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
|
||||
|
||||
/*---------------------------- GPIO Mode Configuration -----------------------*/
|
||||
currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
|
||||
if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
|
||||
/* Output mode */
|
||||
currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
|
||||
}
|
||||
/*---------------------------- GPIO CRL Configuration ------------------------*/
|
||||
/* Configure the eight low port pins */
|
||||
if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
|
||||
{
|
||||
tmpreg = GPIOx->CRL;
|
||||
for (pinpos = 0x00; pinpos < 0x08; pinpos++)
|
||||
{
|
||||
pos = ((uint32_t)0x01) << pinpos;
|
||||
/* Get the port pins position */
|
||||
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
|
||||
if (currentpin == pos)
|
||||
{
|
||||
pos = pinpos << 2;
|
||||
/* Clear the corresponding low control register bits */
|
||||
pinmask = ((uint32_t)0x0F) << pos;
|
||||
tmpreg &= ~pinmask;
|
||||
/* Write the mode configuration in the corresponding bits */
|
||||
tmpreg |= (currentmode << pos);
|
||||
/* Reset the corresponding ODR bit */
|
||||
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
|
||||
{
|
||||
GPIOx->BRR = (((uint32_t)0x01) << pinpos);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set the corresponding ODR bit */
|
||||
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
|
||||
{
|
||||
GPIOx->BSRR = (((uint32_t)0x01) << pinpos);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
GPIOx->CRL = tmpreg;
|
||||
}
|
||||
/*---------------------------- GPIO CRH Configuration ------------------------*/
|
||||
/* Configure the eight high port pins */
|
||||
if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
|
||||
{
|
||||
tmpreg = GPIOx->CRH;
|
||||
for (pinpos = 0x00; pinpos < 0x08; pinpos++)
|
||||
{
|
||||
pos = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||
/* Get the port pins position */
|
||||
currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
|
||||
if (currentpin == pos)
|
||||
{
|
||||
pos = pinpos << 2;
|
||||
/* Clear the corresponding high control register bits */
|
||||
pinmask = ((uint32_t)0x0F) << pos;
|
||||
tmpreg &= ~pinmask;
|
||||
/* Write the mode configuration in the corresponding bits */
|
||||
tmpreg |= (currentmode << pos);
|
||||
/* Reset the corresponding ODR bit */
|
||||
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
|
||||
{
|
||||
GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||
}
|
||||
/* Set the corresponding ODR bit */
|
||||
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
|
||||
{
|
||||
GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||
}
|
||||
}
|
||||
}
|
||||
GPIOx->CRH = tmpreg;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each GPIO_InitStruct member with its default value.
|
||||
* @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
|
||||
{
|
||||
/* Reset GPIO init structure parameters values */
|
||||
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
|
||||
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
|
||||
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified input port pin.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to read.
|
||||
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||
* @retval The input port pin value.
|
||||
*/
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified GPIO input data port.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @retval GPIO input data port value.
|
||||
*/
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
return ((uint16_t)GPIOx->IDR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified output data port bit.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to read.
|
||||
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||
* @retval The output port pin value.
|
||||
*/
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified GPIO output data port.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @retval GPIO output data port value.
|
||||
*/
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
return ((uint16_t)GPIOx->ODR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the selected data port bits.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bits to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
GPIOx->BSRR = GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the selected data port bits.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bits to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
GPIOx->BRR = GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets or clears the selected data port bit.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_Pin_x where x can be (0..15).
|
||||
* @param BitVal: specifies the value to be written to the selected bit.
|
||||
* This parameter can be one of the BitAction enum values:
|
||||
* @arg Bit_RESET: to clear the port pin
|
||||
* @arg Bit_SET: to set the port pin
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
assert_param(IS_GPIO_BIT_ACTION(BitVal));
|
||||
|
||||
if (BitVal != Bit_RESET)
|
||||
{
|
||||
GPIOx->BSRR = GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BRR = GPIO_Pin;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes data to the specified GPIO data port.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param PortVal: specifies the value to be written to the port output data register.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
GPIOx->ODR = PortVal;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks GPIO Pins configuration registers.
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint32_t tmp = 0x00010000;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
tmp |= GPIO_Pin;
|
||||
/* Set LCKK bit */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Reset LCKK bit */
|
||||
GPIOx->LCKR = GPIO_Pin;
|
||||
/* Set LCKK bit */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Read LCKK bit*/
|
||||
tmp = GPIOx->LCKR;
|
||||
/* Read LCKK bit*/
|
||||
tmp = GPIOx->LCKR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the GPIO pin used as Event output.
|
||||
* @param GPIO_PortSource: selects the GPIO port to be used as source
|
||||
* for Event output.
|
||||
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
|
||||
* @param GPIO_PinSource: specifies the pin for the Event output.
|
||||
* This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
|
||||
{
|
||||
uint32_t tmpreg = 0x00;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));
|
||||
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
|
||||
|
||||
tmpreg = AFIO->EVCR;
|
||||
/* Clear the PORT[6:4] and PIN[3:0] bits */
|
||||
tmpreg &= EVCR_PORTPINCONFIG_MASK;
|
||||
tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
|
||||
tmpreg |= GPIO_PinSource;
|
||||
AFIO->EVCR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Event Output.
|
||||
* @param NewState: new state of the Event output.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_EventOutputCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Changes the mapping of the specified pin.
|
||||
* @param GPIO_Remap: selects the pin to remap.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg GPIO_Remap_SPI1 : SPI1 Alternate Function mapping
|
||||
* @arg GPIO_Remap_I2C1 : I2C1 Alternate Function mapping
|
||||
* @arg GPIO_Remap_USART1 : USART1 Alternate Function mapping
|
||||
* @arg GPIO_Remap_USART2 : USART2 Alternate Function mapping
|
||||
* @arg GPIO_PartialRemap_USART3 : USART3 Partial Alternate Function mapping
|
||||
* @arg GPIO_FullRemap_USART3 : USART3 Full Alternate Function mapping
|
||||
* @arg GPIO_PartialRemap_TIM1 : TIM1 Partial Alternate Function mapping
|
||||
* @arg GPIO_FullRemap_TIM1 : TIM1 Full Alternate Function mapping
|
||||
* @arg GPIO_PartialRemap1_TIM2 : TIM2 Partial1 Alternate Function mapping
|
||||
* @arg GPIO_PartialRemap2_TIM2 : TIM2 Partial2 Alternate Function mapping
|
||||
* @arg GPIO_FullRemap_TIM2 : TIM2 Full Alternate Function mapping
|
||||
* @arg GPIO_PartialRemap_TIM3 : TIM3 Partial Alternate Function mapping
|
||||
* @arg GPIO_FullRemap_TIM3 : TIM3 Full Alternate Function mapping
|
||||
* @arg GPIO_Remap_TIM4 : TIM4 Alternate Function mapping
|
||||
* @arg GPIO_Remap1_CAN1 : CAN1 Alternate Function mapping
|
||||
* @arg GPIO_Remap2_CAN1 : CAN1 Alternate Function mapping
|
||||
* @arg GPIO_Remap_PD01 : PD01 Alternate Function mapping
|
||||
* @arg GPIO_Remap_TIM5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibration
|
||||
* @arg GPIO_Remap_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping
|
||||
* @arg GPIO_Remap_ADC1_ETRGREG : ADC1 External Trigger Regular Conversion remapping
|
||||
* @arg GPIO_Remap_ADC2_ETRGINJ : ADC2 External Trigger Injected Conversion remapping
|
||||
* @arg GPIO_Remap_ADC2_ETRGREG : ADC2 External Trigger Regular Conversion remapping
|
||||
* @arg GPIO_Remap_ETH : Ethernet remapping (only for Connectivity line devices)
|
||||
* @arg GPIO_Remap_CAN2 : CAN2 remapping (only for Connectivity line devices)
|
||||
* @arg GPIO_Remap_SWJ_NoJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
|
||||
* @arg GPIO_Remap_SWJ_JTAGDisable : JTAG-DP Disabled and SW-DP Enabled
|
||||
* @arg GPIO_Remap_SWJ_Disable : Full SWJ Disabled (JTAG-DP + SW-DP)
|
||||
* @arg GPIO_Remap_SPI3 : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices)
|
||||
* When the SPI3/I2S3 is remapped using this function, the SWJ is configured
|
||||
* to Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST.
|
||||
* @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected
|
||||
* to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices)
|
||||
* If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to
|
||||
* Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output.
|
||||
* @arg GPIO_Remap_PTP_PPS : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices)
|
||||
* @arg GPIO_Remap_TIM15 : TIM15 Alternate Function mapping (only for Value line devices)
|
||||
* @arg GPIO_Remap_TIM16 : TIM16 Alternate Function mapping (only for Value line devices)
|
||||
* @arg GPIO_Remap_TIM17 : TIM17 Alternate Function mapping (only for Value line devices)
|
||||
* @arg GPIO_Remap_CEC : CEC Alternate Function mapping (only for Value line devices)
|
||||
* @arg GPIO_Remap_TIM1_DMA : TIM1 DMA requests mapping (only for Value line devices)
|
||||
* @arg GPIO_Remap_TIM9 : TIM9 Alternate Function mapping (only for XL-density devices)
|
||||
* @arg GPIO_Remap_TIM10 : TIM10 Alternate Function mapping (only for XL-density devices)
|
||||
* @arg GPIO_Remap_TIM11 : TIM11 Alternate Function mapping (only for XL-density devices)
|
||||
* @arg GPIO_Remap_TIM13 : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices)
|
||||
* @arg GPIO_Remap_TIM14 : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices)
|
||||
* @arg GPIO_Remap_FSMC_NADV : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices)
|
||||
* @arg GPIO_Remap_TIM67_DAC_DMA : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices)
|
||||
* @arg GPIO_Remap_TIM12 : TIM12 Alternate Function mapping (only for High density Value line devices)
|
||||
* @arg GPIO_Remap_MISC : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping,
|
||||
* only for High density Value line devices)
|
||||
* @param NewState: new state of the port pin remapping.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
|
||||
{
|
||||
uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_REMAP(GPIO_Remap));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if((GPIO_Remap & 0x80000000) == 0x80000000)
|
||||
{
|
||||
tmpreg = AFIO->MAPR2;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmpreg = AFIO->MAPR;
|
||||
}
|
||||
|
||||
tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
|
||||
tmp = GPIO_Remap & LSB_MASK;
|
||||
|
||||
if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
|
||||
{
|
||||
tmpreg &= DBGAFR_SWJCFG_MASK;
|
||||
AFIO->MAPR &= DBGAFR_SWJCFG_MASK;
|
||||
}
|
||||
else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
|
||||
{
|
||||
tmp1 = ((uint32_t)0x03) << tmpmask;
|
||||
tmpreg &= ~tmp1;
|
||||
tmpreg |= ~DBGAFR_SWJCFG_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));
|
||||
tmpreg |= ~DBGAFR_SWJCFG_MASK;
|
||||
}
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));
|
||||
}
|
||||
|
||||
if((GPIO_Remap & 0x80000000) == 0x80000000)
|
||||
{
|
||||
AFIO->MAPR2 = tmpreg;
|
||||
}
|
||||
else
|
||||
{
|
||||
AFIO->MAPR = tmpreg;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the GPIO pin used as EXTI Line.
|
||||
* @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines.
|
||||
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
|
||||
* @param GPIO_PinSource: specifies the EXTI line to be configured.
|
||||
* This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
|
||||
{
|
||||
uint32_t tmp = 0x00;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));
|
||||
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
|
||||
|
||||
tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
|
||||
AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
|
||||
AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the Ethernet media interface.
|
||||
* @note This function applies only to STM32 Connectivity line devices.
|
||||
* @param GPIO_ETH_MediaInterface: specifies the Media Interface mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg GPIO_ETH_MediaInterface_MII: MII mode
|
||||
* @arg GPIO_ETH_MediaInterface_RMII: RMII mode
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface)
|
||||
{
|
||||
assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface));
|
||||
|
||||
/* Configure MII_RMII selection bit */
|
||||
*(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,385 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the GPIO
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_GPIO_H
|
||||
#define __STM32F10x_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
|
||||
((PERIPH) == GPIOB) || \
|
||||
((PERIPH) == GPIOC) || \
|
||||
((PERIPH) == GPIOD) || \
|
||||
((PERIPH) == GPIOE) || \
|
||||
((PERIPH) == GPIOF) || \
|
||||
((PERIPH) == GPIOG))
|
||||
|
||||
/**
|
||||
* @brief Output Maximum frequency selection
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Speed_10MHz = 1,
|
||||
GPIO_Speed_2MHz,
|
||||
GPIO_Speed_50MHz
|
||||
}GPIOSpeed_TypeDef;
|
||||
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \
|
||||
((SPEED) == GPIO_Speed_50MHz))
|
||||
|
||||
/**
|
||||
* @brief Configuration Mode enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{ GPIO_Mode_AIN = 0x0,
|
||||
GPIO_Mode_IN_FLOATING = 0x04,
|
||||
GPIO_Mode_IPD = 0x28,
|
||||
GPIO_Mode_IPU = 0x48,
|
||||
GPIO_Mode_Out_OD = 0x14,
|
||||
GPIO_Mode_Out_PP = 0x10,
|
||||
GPIO_Mode_AF_OD = 0x1C,
|
||||
GPIO_Mode_AF_PP = 0x18
|
||||
}GPIOMode_TypeDef;
|
||||
|
||||
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \
|
||||
((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \
|
||||
((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \
|
||||
((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))
|
||||
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */
|
||||
|
||||
GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIOSpeed_TypeDef */
|
||||
|
||||
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIOMode_TypeDef */
|
||||
}GPIO_InitTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Bit_SET and Bit_RESET enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{ Bit_RESET = 0,
|
||||
Bit_SET
|
||||
}BitAction;
|
||||
|
||||
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pins_define
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
|
||||
#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
|
||||
#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
|
||||
#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
|
||||
#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
|
||||
#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
|
||||
#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
|
||||
#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
|
||||
#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
|
||||
#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
|
||||
#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
|
||||
#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
|
||||
#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
|
||||
#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
|
||||
#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
|
||||
#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
|
||||
#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
|
||||
|
||||
#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
|
||||
|
||||
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
|
||||
((PIN) == GPIO_Pin_1) || \
|
||||
((PIN) == GPIO_Pin_2) || \
|
||||
((PIN) == GPIO_Pin_3) || \
|
||||
((PIN) == GPIO_Pin_4) || \
|
||||
((PIN) == GPIO_Pin_5) || \
|
||||
((PIN) == GPIO_Pin_6) || \
|
||||
((PIN) == GPIO_Pin_7) || \
|
||||
((PIN) == GPIO_Pin_8) || \
|
||||
((PIN) == GPIO_Pin_9) || \
|
||||
((PIN) == GPIO_Pin_10) || \
|
||||
((PIN) == GPIO_Pin_11) || \
|
||||
((PIN) == GPIO_Pin_12) || \
|
||||
((PIN) == GPIO_Pin_13) || \
|
||||
((PIN) == GPIO_Pin_14) || \
|
||||
((PIN) == GPIO_Pin_15))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Remap_define
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */
|
||||
#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */
|
||||
#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */
|
||||
#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */
|
||||
#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */
|
||||
#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */
|
||||
#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */
|
||||
#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */
|
||||
#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */
|
||||
#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */
|
||||
#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */
|
||||
#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */
|
||||
#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */
|
||||
#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */
|
||||
#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */
|
||||
#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */
|
||||
#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */
|
||||
#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */
|
||||
#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */
|
||||
#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */
|
||||
#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */
|
||||
#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */
|
||||
#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
|
||||
#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */
|
||||
#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
|
||||
#define GPIO_Remap_SPI3 ((uint32_t)0x00201100) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
|
||||
#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected
|
||||
to TIM2 Internal Trigger 1 for calibration
|
||||
(only for Connectivity line devices) */
|
||||
#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
|
||||
|
||||
#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */
|
||||
#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */
|
||||
#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */
|
||||
#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */
|
||||
#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */
|
||||
|
||||
#define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */
|
||||
#define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */
|
||||
#define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */
|
||||
#define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */
|
||||
#define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */
|
||||
#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */
|
||||
|
||||
#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */
|
||||
#define GPIO_Remap_TIM12 ((uint32_t)0x80001000) /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */
|
||||
#define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping,
|
||||
only for High density Value line devices) */
|
||||
|
||||
#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \
|
||||
((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \
|
||||
((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \
|
||||
((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \
|
||||
((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \
|
||||
((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \
|
||||
((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \
|
||||
((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \
|
||||
((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \
|
||||
((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \
|
||||
((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \
|
||||
((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \
|
||||
((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \
|
||||
((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \
|
||||
((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \
|
||||
((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \
|
||||
((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \
|
||||
((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \
|
||||
((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \
|
||||
((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \
|
||||
((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \
|
||||
((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Port_Sources
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
|
||||
#define GPIO_PortSourceGPIOB ((uint8_t)0x01)
|
||||
#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
|
||||
#define GPIO_PortSourceGPIOD ((uint8_t)0x03)
|
||||
#define GPIO_PortSourceGPIOE ((uint8_t)0x04)
|
||||
#define GPIO_PortSourceGPIOF ((uint8_t)0x05)
|
||||
#define GPIO_PortSourceGPIOG ((uint8_t)0x06)
|
||||
#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOE))
|
||||
|
||||
#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOE) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOF) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOG))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Pin_sources
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_PinSource0 ((uint8_t)0x00)
|
||||
#define GPIO_PinSource1 ((uint8_t)0x01)
|
||||
#define GPIO_PinSource2 ((uint8_t)0x02)
|
||||
#define GPIO_PinSource3 ((uint8_t)0x03)
|
||||
#define GPIO_PinSource4 ((uint8_t)0x04)
|
||||
#define GPIO_PinSource5 ((uint8_t)0x05)
|
||||
#define GPIO_PinSource6 ((uint8_t)0x06)
|
||||
#define GPIO_PinSource7 ((uint8_t)0x07)
|
||||
#define GPIO_PinSource8 ((uint8_t)0x08)
|
||||
#define GPIO_PinSource9 ((uint8_t)0x09)
|
||||
#define GPIO_PinSource10 ((uint8_t)0x0A)
|
||||
#define GPIO_PinSource11 ((uint8_t)0x0B)
|
||||
#define GPIO_PinSource12 ((uint8_t)0x0C)
|
||||
#define GPIO_PinSource13 ((uint8_t)0x0D)
|
||||
#define GPIO_PinSource14 ((uint8_t)0x0E)
|
||||
#define GPIO_PinSource15 ((uint8_t)0x0F)
|
||||
|
||||
#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
|
||||
((PINSOURCE) == GPIO_PinSource1) || \
|
||||
((PINSOURCE) == GPIO_PinSource2) || \
|
||||
((PINSOURCE) == GPIO_PinSource3) || \
|
||||
((PINSOURCE) == GPIO_PinSource4) || \
|
||||
((PINSOURCE) == GPIO_PinSource5) || \
|
||||
((PINSOURCE) == GPIO_PinSource6) || \
|
||||
((PINSOURCE) == GPIO_PinSource7) || \
|
||||
((PINSOURCE) == GPIO_PinSource8) || \
|
||||
((PINSOURCE) == GPIO_PinSource9) || \
|
||||
((PINSOURCE) == GPIO_PinSource10) || \
|
||||
((PINSOURCE) == GPIO_PinSource11) || \
|
||||
((PINSOURCE) == GPIO_PinSource12) || \
|
||||
((PINSOURCE) == GPIO_PinSource13) || \
|
||||
((PINSOURCE) == GPIO_PinSource14) || \
|
||||
((PINSOURCE) == GPIO_PinSource15))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Ethernet_Media_Interface
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000)
|
||||
#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001)
|
||||
|
||||
#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \
|
||||
((INTERFACE) == GPIO_ETH_MediaInterface_RMII))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
|
||||
void GPIO_AFIODeInit(void);
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
|
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
|
||||
void GPIO_EventOutputCmd(FunctionalState NewState);
|
||||
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
|
||||
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
|
||||
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_GPIO_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,684 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the I2C firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_I2C_H
|
||||
#define __STM32F10x_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief I2C Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
|
||||
This parameter must be set to a value lower than 400kHz */
|
||||
|
||||
uint16_t I2C_Mode; /*!< Specifies the I2C mode.
|
||||
This parameter can be a value of @ref I2C_mode */
|
||||
|
||||
uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
|
||||
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
|
||||
|
||||
uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
|
||||
This parameter can be a value of @ref I2C_acknowledgement */
|
||||
|
||||
uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
|
||||
This parameter can be a value of @ref I2C_acknowledged_address */
|
||||
}I2C_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup I2C_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
|
||||
((PERIPH) == I2C2))
|
||||
/** @defgroup I2C_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Mode_I2C ((uint16_t)0x0000)
|
||||
#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
|
||||
#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
|
||||
#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
|
||||
((MODE) == I2C_Mode_SMBusDevice) || \
|
||||
((MODE) == I2C_Mode_SMBusHost))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_duty_cycle_in_fast_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
|
||||
#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
|
||||
#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
|
||||
((CYCLE) == I2C_DutyCycle_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_acknowledgement
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Ack_Enable ((uint16_t)0x0400)
|
||||
#define I2C_Ack_Disable ((uint16_t)0x0000)
|
||||
#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
|
||||
((STATE) == I2C_Ack_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_transfer_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Direction_Transmitter ((uint8_t)0x00)
|
||||
#define I2C_Direction_Receiver ((uint8_t)0x01)
|
||||
#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
|
||||
((DIRECTION) == I2C_Direction_Receiver))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_acknowledged_address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
|
||||
#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
|
||||
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
|
||||
((ADDRESS) == I2C_AcknowledgedAddress_10bit))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_registers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Register_CR1 ((uint8_t)0x00)
|
||||
#define I2C_Register_CR2 ((uint8_t)0x04)
|
||||
#define I2C_Register_OAR1 ((uint8_t)0x08)
|
||||
#define I2C_Register_OAR2 ((uint8_t)0x0C)
|
||||
#define I2C_Register_DR ((uint8_t)0x10)
|
||||
#define I2C_Register_SR1 ((uint8_t)0x14)
|
||||
#define I2C_Register_SR2 ((uint8_t)0x18)
|
||||
#define I2C_Register_CCR ((uint8_t)0x1C)
|
||||
#define I2C_Register_TRISE ((uint8_t)0x20)
|
||||
#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
|
||||
((REGISTER) == I2C_Register_CR2) || \
|
||||
((REGISTER) == I2C_Register_OAR1) || \
|
||||
((REGISTER) == I2C_Register_OAR2) || \
|
||||
((REGISTER) == I2C_Register_DR) || \
|
||||
((REGISTER) == I2C_Register_SR1) || \
|
||||
((REGISTER) == I2C_Register_SR2) || \
|
||||
((REGISTER) == I2C_Register_CCR) || \
|
||||
((REGISTER) == I2C_Register_TRISE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_SMBus_alert_pin_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
|
||||
#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
|
||||
#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
|
||||
((ALERT) == I2C_SMBusAlert_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_PEC_position
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_PECPosition_Next ((uint16_t)0x0800)
|
||||
#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
|
||||
#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
|
||||
((POSITION) == I2C_PECPosition_Current))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_NCAK_position
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_NACKPosition_Next ((uint16_t)0x0800)
|
||||
#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
|
||||
#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \
|
||||
((POSITION) == I2C_NACKPosition_Current))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_IT_BUF ((uint16_t)0x0400)
|
||||
#define I2C_IT_EVT ((uint16_t)0x0200)
|
||||
#define I2C_IT_ERR ((uint16_t)0x0100)
|
||||
#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
|
||||
#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
|
||||
#define I2C_IT_PECERR ((uint32_t)0x01001000)
|
||||
#define I2C_IT_OVR ((uint32_t)0x01000800)
|
||||
#define I2C_IT_AF ((uint32_t)0x01000400)
|
||||
#define I2C_IT_ARLO ((uint32_t)0x01000200)
|
||||
#define I2C_IT_BERR ((uint32_t)0x01000100)
|
||||
#define I2C_IT_TXE ((uint32_t)0x06000080)
|
||||
#define I2C_IT_RXNE ((uint32_t)0x06000040)
|
||||
#define I2C_IT_STOPF ((uint32_t)0x02000010)
|
||||
#define I2C_IT_ADD10 ((uint32_t)0x02000008)
|
||||
#define I2C_IT_BTF ((uint32_t)0x02000004)
|
||||
#define I2C_IT_ADDR ((uint32_t)0x02000002)
|
||||
#define I2C_IT_SB ((uint32_t)0x02000001)
|
||||
|
||||
#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
|
||||
|
||||
#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
|
||||
((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
|
||||
((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
|
||||
((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
|
||||
((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
|
||||
((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
|
||||
((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SR2 register flags
|
||||
*/
|
||||
|
||||
#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
|
||||
#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
|
||||
#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
|
||||
#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
|
||||
#define I2C_FLAG_TRA ((uint32_t)0x00040000)
|
||||
#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
|
||||
#define I2C_FLAG_MSL ((uint32_t)0x00010000)
|
||||
|
||||
/**
|
||||
* @brief SR1 register flags
|
||||
*/
|
||||
|
||||
#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
|
||||
#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
|
||||
#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
|
||||
#define I2C_FLAG_OVR ((uint32_t)0x10000800)
|
||||
#define I2C_FLAG_AF ((uint32_t)0x10000400)
|
||||
#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
|
||||
#define I2C_FLAG_BERR ((uint32_t)0x10000100)
|
||||
#define I2C_FLAG_TXE ((uint32_t)0x10000080)
|
||||
#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
|
||||
#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
|
||||
#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
|
||||
#define I2C_FLAG_BTF ((uint32_t)0x10000004)
|
||||
#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
|
||||
#define I2C_FLAG_SB ((uint32_t)0x10000001)
|
||||
|
||||
#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
|
||||
|
||||
#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
|
||||
((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
|
||||
((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
|
||||
((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
|
||||
((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
|
||||
((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
|
||||
((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
|
||||
((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
|
||||
((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
|
||||
((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
|
||||
((FLAG) == I2C_FLAG_SB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Events
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*========================================
|
||||
|
||||
I2C Master Events (Events grouped in order of communication)
|
||||
==========================================*/
|
||||
/**
|
||||
* @brief Communication start
|
||||
*
|
||||
* After sending the START condition (I2C_GenerateSTART() function) the master
|
||||
* has to wait for this event. It means that the Start condition has been correctly
|
||||
* released on the I2C bus (the bus is free, no other devices is communicating).
|
||||
*
|
||||
*/
|
||||
/* --EV5 */
|
||||
#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
|
||||
|
||||
/**
|
||||
* @brief Address Acknowledge
|
||||
*
|
||||
* After checking on EV5 (start condition correctly released on the bus), the
|
||||
* master sends the address of the slave(s) with which it will communicate
|
||||
* (I2C_Send7bitAddress() function, it also determines the direction of the communication:
|
||||
* Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
|
||||
* his address. If an acknowledge is sent on the bus, one of the following events will
|
||||
* be set:
|
||||
*
|
||||
* 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
|
||||
* event is set.
|
||||
*
|
||||
* 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
|
||||
* is set
|
||||
*
|
||||
* 3) In case of 10-Bit addressing mode, the master (just after generating the START
|
||||
* and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
|
||||
* function). Then master should wait on EV9. It means that the 10-bit addressing
|
||||
* header has been correctly sent on the bus. Then master should send the second part of
|
||||
* the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
|
||||
* should wait for event EV6.
|
||||
*
|
||||
*/
|
||||
|
||||
/* --EV6 */
|
||||
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
|
||||
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
|
||||
/* --EV9 */
|
||||
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
|
||||
|
||||
/**
|
||||
* @brief Communication events
|
||||
*
|
||||
* If a communication is established (START condition generated and slave address
|
||||
* acknowledged) then the master has to check on one of the following events for
|
||||
* communication procedures:
|
||||
*
|
||||
* 1) Master Receiver mode: The master has to wait on the event EV7 then to read
|
||||
* the data received from the slave (I2C_ReceiveData() function).
|
||||
*
|
||||
* 2) Master Transmitter mode: The master has to send data (I2C_SendData()
|
||||
* function) then to wait on event EV8 or EV8_2.
|
||||
* These two events are similar:
|
||||
* - EV8 means that the data has been written in the data register and is
|
||||
* being shifted out.
|
||||
* - EV8_2 means that the data has been physically shifted out and output
|
||||
* on the bus.
|
||||
* In most cases, using EV8 is sufficient for the application.
|
||||
* Using EV8_2 leads to a slower communication but ensure more reliable test.
|
||||
* EV8_2 is also more suitable than EV8 for testing on the last data transmission
|
||||
* (before Stop condition generation).
|
||||
*
|
||||
* @note In case the user software does not guarantee that this event EV7 is
|
||||
* managed before the current byte end of transfer, then user may check on EV7
|
||||
* and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
|
||||
* In this case the communication may be slower.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Master RECEIVER mode -----------------------------*/
|
||||
/* --EV7 */
|
||||
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
|
||||
|
||||
/* Master TRANSMITTER mode --------------------------*/
|
||||
/* --EV8 */
|
||||
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
|
||||
/* --EV8_2 */
|
||||
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
|
||||
|
||||
|
||||
/*========================================
|
||||
|
||||
I2C Slave Events (Events grouped in order of communication)
|
||||
==========================================*/
|
||||
|
||||
/**
|
||||
* @brief Communication start events
|
||||
*
|
||||
* Wait on one of these events at the start of the communication. It means that
|
||||
* the I2C peripheral detected a Start condition on the bus (generated by master
|
||||
* device) followed by the peripheral address. The peripheral generates an ACK
|
||||
* condition on the bus (if the acknowledge feature is enabled through function
|
||||
* I2C_AcknowledgeConfig()) and the events listed above are set :
|
||||
*
|
||||
* 1) In normal case (only one address managed by the slave), when the address
|
||||
* sent by the master matches the own address of the peripheral (configured by
|
||||
* I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
|
||||
* (where XXX could be TRANSMITTER or RECEIVER).
|
||||
*
|
||||
* 2) In case the address sent by the master matches the second address of the
|
||||
* peripheral (configured by the function I2C_OwnAddress2Config() and enabled
|
||||
* by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
|
||||
* (where XXX could be TRANSMITTER or RECEIVER) are set.
|
||||
*
|
||||
* 3) In case the address sent by the master is General Call (address 0x00) and
|
||||
* if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
|
||||
* the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
|
||||
*
|
||||
*/
|
||||
|
||||
/* --EV1 (all the events below are variants of EV1) */
|
||||
/* 1) Case of One Single Address managed by the slave */
|
||||
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
|
||||
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
|
||||
|
||||
/* 2) Case of Dual address managed by the slave */
|
||||
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
|
||||
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
|
||||
|
||||
/* 3) Case of General Call enabled for the slave */
|
||||
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
|
||||
|
||||
/**
|
||||
* @brief Communication events
|
||||
*
|
||||
* Wait on one of these events when EV1 has already been checked and:
|
||||
*
|
||||
* - Slave RECEIVER mode:
|
||||
* - EV2: When the application is expecting a data byte to be received.
|
||||
* - EV4: When the application is expecting the end of the communication: master
|
||||
* sends a stop condition and data transmission is stopped.
|
||||
*
|
||||
* - Slave Transmitter mode:
|
||||
* - EV3: When a byte has been transmitted by the slave and the application is expecting
|
||||
* the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
|
||||
* I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
|
||||
* used when the user software doesn't guarantee the EV3 is managed before the
|
||||
* current byte end of transfer.
|
||||
* - EV3_2: When the master sends a NACK in order to tell slave that data transmission
|
||||
* shall end (before sending the STOP condition). In this case slave has to stop sending
|
||||
* data bytes and expect a Stop condition on the bus.
|
||||
*
|
||||
* @note In case the user software does not guarantee that the event EV2 is
|
||||
* managed before the current byte end of transfer, then user may check on EV2
|
||||
* and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
|
||||
* In this case the communication may be slower.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Slave RECEIVER mode --------------------------*/
|
||||
/* --EV2 */
|
||||
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
|
||||
/* --EV4 */
|
||||
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
|
||||
|
||||
/* Slave TRANSMITTER mode -----------------------*/
|
||||
/* --EV3 */
|
||||
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
|
||||
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
|
||||
/* --EV3_2 */
|
||||
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
|
||||
|
||||
/*=========================== End of Events Description ==========================================*/
|
||||
|
||||
#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
|
||||
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
|
||||
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
|
||||
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
|
||||
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_own_address1
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_clock_speed
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void I2C_DeInit(I2C_TypeDef* I2Cx);
|
||||
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
|
||||
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
|
||||
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
|
||||
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
|
||||
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
|
||||
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
|
||||
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
|
||||
uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
|
||||
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
|
||||
void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
|
||||
void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
|
||||
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
|
||||
void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
|
||||
|
||||
/**
|
||||
* @brief
|
||||
****************************************************************************************
|
||||
*
|
||||
* I2C State Monitoring Functions
|
||||
*
|
||||
****************************************************************************************
|
||||
* This I2C driver provides three different ways for I2C state monitoring
|
||||
* depending on the application requirements and constraints:
|
||||
*
|
||||
*
|
||||
* 1) Basic state monitoring:
|
||||
* Using I2C_CheckEvent() function:
|
||||
* It compares the status registers (SR1 and SR2) content to a given event
|
||||
* (can be the combination of one or more flags).
|
||||
* It returns SUCCESS if the current status includes the given flags
|
||||
* and returns ERROR if one or more flags are missing in the current status.
|
||||
* - When to use:
|
||||
* - This function is suitable for most applications as well as for startup
|
||||
* activity since the events are fully described in the product reference manual
|
||||
* (RM0008).
|
||||
* - It is also suitable for users who need to define their own events.
|
||||
* - Limitations:
|
||||
* - If an error occurs (ie. error flags are set besides to the monitored flags),
|
||||
* the I2C_CheckEvent() function may return SUCCESS despite the communication
|
||||
* hold or corrupted real state.
|
||||
* In this case, it is advised to use error interrupts to monitor the error
|
||||
* events and handle them in the interrupt IRQ handler.
|
||||
*
|
||||
* @note
|
||||
* For error management, it is advised to use the following functions:
|
||||
* - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
|
||||
* - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
|
||||
* Where x is the peripheral instance (I2C1, I2C2 ...)
|
||||
* - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
|
||||
* in order to determine which error occurred.
|
||||
* - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
|
||||
* and/or I2C_GenerateStop() in order to clear the error flag and source,
|
||||
* and return to correct communication status.
|
||||
*
|
||||
*
|
||||
* 2) Advanced state monitoring:
|
||||
* Using the function I2C_GetLastEvent() which returns the image of both status
|
||||
* registers in a single word (uint32_t) (Status Register 2 value is shifted left
|
||||
* by 16 bits and concatenated to Status Register 1).
|
||||
* - When to use:
|
||||
* - This function is suitable for the same applications above but it allows to
|
||||
* overcome the limitations of I2C_GetFlagStatus() function (see below).
|
||||
* The returned value could be compared to events already defined in the
|
||||
* library (stm32f10x_i2c.h) or to custom values defined by user.
|
||||
* - This function is suitable when multiple flags are monitored at the same time.
|
||||
* - At the opposite of I2C_CheckEvent() function, this function allows user to
|
||||
* choose when an event is accepted (when all events flags are set and no
|
||||
* other flags are set or just when the needed flags are set like
|
||||
* I2C_CheckEvent() function).
|
||||
* - Limitations:
|
||||
* - User may need to define his own events.
|
||||
* - Same remark concerning the error management is applicable for this
|
||||
* function if user decides to check only regular communication flags (and
|
||||
* ignores error flags).
|
||||
*
|
||||
*
|
||||
* 3) Flag-based state monitoring:
|
||||
* Using the function I2C_GetFlagStatus() which simply returns the status of
|
||||
* one single flag (ie. I2C_FLAG_RXNE ...).
|
||||
* - When to use:
|
||||
* - This function could be used for specific applications or in debug phase.
|
||||
* - It is suitable when only one flag checking is needed (most I2C events
|
||||
* are monitored through multiple flags).
|
||||
* - Limitations:
|
||||
* - When calling this function, the Status register is accessed. Some flags are
|
||||
* cleared when the status register is accessed. So checking the status
|
||||
* of one Flag, may clear other ones.
|
||||
* - Function may need to be called twice or more in order to monitor one
|
||||
* single event.
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
*
|
||||
* 1) Basic state monitoring
|
||||
*******************************************************************************
|
||||
*/
|
||||
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
|
||||
/**
|
||||
*
|
||||
* 2) Advanced state monitoring
|
||||
*******************************************************************************
|
||||
*/
|
||||
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
|
||||
/**
|
||||
*
|
||||
* 3) Flag-based state monitoring
|
||||
*******************************************************************************
|
||||
*/
|
||||
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||
/**
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
|
||||
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F10x_I2C_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,190 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_iwdg.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the IWDG firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_iwdg.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG
|
||||
* @brief IWDG driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ---------------------- IWDG registers bit mask ----------------------------*/
|
||||
|
||||
/* KR register bit mask */
|
||||
#define KR_KEY_Reload ((uint16_t)0xAAAA)
|
||||
#define KR_KEY_Enable ((uint16_t)0xCCCC)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
|
||||
* @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
|
||||
* @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
|
||||
IWDG->KR = IWDG_WriteAccess;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets IWDG Prescaler value.
|
||||
* @param IWDG_Prescaler: specifies the IWDG Prescaler value.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IWDG_Prescaler_4: IWDG prescaler set to 4
|
||||
* @arg IWDG_Prescaler_8: IWDG prescaler set to 8
|
||||
* @arg IWDG_Prescaler_16: IWDG prescaler set to 16
|
||||
* @arg IWDG_Prescaler_32: IWDG prescaler set to 32
|
||||
* @arg IWDG_Prescaler_64: IWDG prescaler set to 64
|
||||
* @arg IWDG_Prescaler_128: IWDG prescaler set to 128
|
||||
* @arg IWDG_Prescaler_256: IWDG prescaler set to 256
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
|
||||
IWDG->PR = IWDG_Prescaler;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets IWDG Reload value.
|
||||
* @param Reload: specifies the IWDG Reload value.
|
||||
* This parameter must be a number between 0 and 0x0FFF.
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_SetReload(uint16_t Reload)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_RELOAD(Reload));
|
||||
IWDG->RLR = Reload;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reloads IWDG counter with value defined in the reload register
|
||||
* (write access to IWDG_PR and IWDG_RLR registers disabled).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_ReloadCounter(void)
|
||||
{
|
||||
IWDG->KR = KR_KEY_Reload;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_Enable(void)
|
||||
{
|
||||
IWDG->KR = KR_KEY_Enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified IWDG flag is set or not.
|
||||
* @param IWDG_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IWDG_FLAG_PVU: Prescaler Value Update on going
|
||||
* @arg IWDG_FLAG_RVU: Reload Value Update on going
|
||||
* @retval The new state of IWDG_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_FLAG(IWDG_FLAG));
|
||||
if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the flag status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,140 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_iwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the IWDG
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_IWDG_H
|
||||
#define __STM32F10x_IWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_WriteAccess
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
|
||||
#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
|
||||
#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
|
||||
((ACCESS) == IWDG_WriteAccess_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IWDG_Prescaler_4 ((uint8_t)0x00)
|
||||
#define IWDG_Prescaler_8 ((uint8_t)0x01)
|
||||
#define IWDG_Prescaler_16 ((uint8_t)0x02)
|
||||
#define IWDG_Prescaler_32 ((uint8_t)0x03)
|
||||
#define IWDG_Prescaler_64 ((uint8_t)0x04)
|
||||
#define IWDG_Prescaler_128 ((uint8_t)0x05)
|
||||
#define IWDG_Prescaler_256 ((uint8_t)0x06)
|
||||
#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
|
||||
((PRESCALER) == IWDG_Prescaler_8) || \
|
||||
((PRESCALER) == IWDG_Prescaler_16) || \
|
||||
((PRESCALER) == IWDG_Prescaler_32) || \
|
||||
((PRESCALER) == IWDG_Prescaler_64) || \
|
||||
((PRESCALER) == IWDG_Prescaler_128)|| \
|
||||
((PRESCALER) == IWDG_Prescaler_256))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IWDG_FLAG_PVU ((uint16_t)0x0001)
|
||||
#define IWDG_FLAG_RVU ((uint16_t)0x0002)
|
||||
#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
|
||||
#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
|
||||
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
|
||||
void IWDG_SetReload(uint16_t Reload);
|
||||
void IWDG_ReloadCounter(void);
|
||||
void IWDG_Enable(void);
|
||||
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_IWDG_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,307 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_pwr.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the PWR firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_pwr.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR
|
||||
* @brief PWR driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* --------- PWR registers bit address in the alias region ---------- */
|
||||
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
|
||||
|
||||
/* --- CR Register ---*/
|
||||
|
||||
/* Alias word address of DBP bit */
|
||||
#define CR_OFFSET (PWR_OFFSET + 0x00)
|
||||
#define DBP_BitNumber 0x08
|
||||
#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
|
||||
|
||||
/* Alias word address of PVDE bit */
|
||||
#define PVDE_BitNumber 0x04
|
||||
#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
|
||||
|
||||
/* --- CSR Register ---*/
|
||||
|
||||
/* Alias word address of EWUP bit */
|
||||
#define CSR_OFFSET (PWR_OFFSET + 0x04)
|
||||
#define EWUP_BitNumber 0x08
|
||||
#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
|
||||
|
||||
/* ------------------ PWR registers bit mask ------------------------ */
|
||||
|
||||
/* CR register bit mask */
|
||||
#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
|
||||
#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the PWR peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_DeInit(void)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables access to the RTC and backup registers.
|
||||
* @param NewState: new state of the access to the RTC and backup registers.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_BackupAccessCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Power Voltage Detector(PVD).
|
||||
* @param NewState: new state of the PVD.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_PVDCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
|
||||
* @param PWR_PVDLevel: specifies the PVD detection level
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V
|
||||
* @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V
|
||||
* @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
|
||||
* @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V
|
||||
* @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
|
||||
* @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
|
||||
* @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
|
||||
* @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
|
||||
tmpreg = PWR->CR;
|
||||
/* Clear PLS[7:5] bits */
|
||||
tmpreg &= CR_PLS_MASK;
|
||||
/* Set PLS[7:5] bits according to PWR_PVDLevel value */
|
||||
tmpreg |= PWR_PVDLevel;
|
||||
/* Store the new value */
|
||||
PWR->CR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the WakeUp Pin functionality.
|
||||
* @param NewState: new state of the WakeUp Pin functionality.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_WakeUpPinCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
*(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters STOP mode.
|
||||
* @param PWR_Regulator: specifies the regulator state in STOP mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_Regulator_ON: STOP mode with regulator ON
|
||||
* @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
|
||||
* @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
|
||||
* @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(PWR_Regulator));
|
||||
assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
|
||||
|
||||
/* Select the regulator state in STOP mode ---------------------------------*/
|
||||
tmpreg = PWR->CR;
|
||||
/* Clear PDDS and LPDS bits */
|
||||
tmpreg &= CR_DS_MASK;
|
||||
/* Set LPDS bit according to PWR_Regulator value */
|
||||
tmpreg |= PWR_Regulator;
|
||||
/* Store the new value */
|
||||
PWR->CR = tmpreg;
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP;
|
||||
|
||||
/* Select STOP mode entry --------------------------------------------------*/
|
||||
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__WFE();
|
||||
}
|
||||
|
||||
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters STANDBY mode.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_EnterSTANDBYMode(void)
|
||||
{
|
||||
/* Clear Wake-up flag */
|
||||
PWR->CR |= PWR_CR_CWUF;
|
||||
/* Select STANDBY mode */
|
||||
PWR->CR |= PWR_CR_PDDS;
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP;
|
||||
/* This option is used to ensure that store operations are completed */
|
||||
#if defined ( __CC_ARM )
|
||||
__force_stores();
|
||||
#endif
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified PWR flag is set or not.
|
||||
* @param PWR_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_WU: Wake Up flag
|
||||
* @arg PWR_FLAG_SB: StandBy flag
|
||||
* @arg PWR_FLAG_PVDO: PVD Output
|
||||
* @retval The new state of PWR_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
|
||||
|
||||
if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the flag status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the PWR's pending flags.
|
||||
* @param PWR_FLAG: specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_WU: Wake Up flag
|
||||
* @arg PWR_FLAG_SB: StandBy flag
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_ClearFlag(uint32_t PWR_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
|
||||
|
||||
PWR->CR |= PWR_FLAG << 2;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,156 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the PWR firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_PWR_H
|
||||
#define __STM32F10x_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PVD_detection_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)
|
||||
#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)
|
||||
#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040)
|
||||
#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060)
|
||||
#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080)
|
||||
#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)
|
||||
#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)
|
||||
#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)
|
||||
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \
|
||||
((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \
|
||||
((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \
|
||||
((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Regulator_state_is_STOP_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_Regulator_ON ((uint32_t)0x00000000)
|
||||
#define PWR_Regulator_LowPower ((uint32_t)0x00000001)
|
||||
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
|
||||
((REGULATOR) == PWR_Regulator_LowPower))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STOP_mode_entry
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
|
||||
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
|
||||
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_FLAG_WU ((uint32_t)0x00000001)
|
||||
#define PWR_FLAG_SB ((uint32_t)0x00000002)
|
||||
#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
|
||||
#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
|
||||
((FLAG) == PWR_FLAG_PVDO))
|
||||
|
||||
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void PWR_DeInit(void);
|
||||
void PWR_BackupAccessCmd(FunctionalState NewState);
|
||||
void PWR_PVDCmd(FunctionalState NewState);
|
||||
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
|
||||
void PWR_WakeUpPinCmd(FunctionalState NewState);
|
||||
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
|
||||
void PWR_EnterSTANDBYMode(void);
|
||||
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
|
||||
void PWR_ClearFlag(uint32_t PWR_FLAG);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_PWR_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,727 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_rcc.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the RCC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_RCC_H
|
||||
#define __STM32F10x_RCC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */
|
||||
uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */
|
||||
uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */
|
||||
uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */
|
||||
uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */
|
||||
}RCC_ClocksTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HSE_configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_HSE_OFF ((uint32_t)0x00000000)
|
||||
#define RCC_HSE_ON ((uint32_t)0x00010000)
|
||||
#define RCC_HSE_Bypass ((uint32_t)0x00040000)
|
||||
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
|
||||
((HSE) == RCC_HSE_Bypass))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PLL_entry_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)
|
||||
|
||||
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL)
|
||||
#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
|
||||
#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
|
||||
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
|
||||
((SOURCE) == RCC_PLLSource_HSE_Div1) || \
|
||||
((SOURCE) == RCC_PLLSource_HSE_Div2))
|
||||
#else
|
||||
#define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000)
|
||||
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
|
||||
((SOURCE) == RCC_PLLSource_PREDIV1))
|
||||
#endif /* STM32F10X_CL */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PLL_multiplication_factor
|
||||
* @{
|
||||
*/
|
||||
#ifndef STM32F10X_CL
|
||||
#define RCC_PLLMul_2 ((uint32_t)0x00000000)
|
||||
#define RCC_PLLMul_3 ((uint32_t)0x00040000)
|
||||
#define RCC_PLLMul_4 ((uint32_t)0x00080000)
|
||||
#define RCC_PLLMul_5 ((uint32_t)0x000C0000)
|
||||
#define RCC_PLLMul_6 ((uint32_t)0x00100000)
|
||||
#define RCC_PLLMul_7 ((uint32_t)0x00140000)
|
||||
#define RCC_PLLMul_8 ((uint32_t)0x00180000)
|
||||
#define RCC_PLLMul_9 ((uint32_t)0x001C0000)
|
||||
#define RCC_PLLMul_10 ((uint32_t)0x00200000)
|
||||
#define RCC_PLLMul_11 ((uint32_t)0x00240000)
|
||||
#define RCC_PLLMul_12 ((uint32_t)0x00280000)
|
||||
#define RCC_PLLMul_13 ((uint32_t)0x002C0000)
|
||||
#define RCC_PLLMul_14 ((uint32_t)0x00300000)
|
||||
#define RCC_PLLMul_15 ((uint32_t)0x00340000)
|
||||
#define RCC_PLLMul_16 ((uint32_t)0x00380000)
|
||||
#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
|
||||
((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
|
||||
((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
|
||||
((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
|
||||
((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
|
||||
((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
|
||||
((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
|
||||
((MUL) == RCC_PLLMul_16))
|
||||
|
||||
#else
|
||||
#define RCC_PLLMul_4 ((uint32_t)0x00080000)
|
||||
#define RCC_PLLMul_5 ((uint32_t)0x000C0000)
|
||||
#define RCC_PLLMul_6 ((uint32_t)0x00100000)
|
||||
#define RCC_PLLMul_7 ((uint32_t)0x00140000)
|
||||
#define RCC_PLLMul_8 ((uint32_t)0x00180000)
|
||||
#define RCC_PLLMul_9 ((uint32_t)0x001C0000)
|
||||
#define RCC_PLLMul_6_5 ((uint32_t)0x00340000)
|
||||
|
||||
#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
|
||||
((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
|
||||
((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
|
||||
((MUL) == RCC_PLLMul_6_5))
|
||||
#endif /* STM32F10X_CL */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PREDIV1_division_factor
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
|
||||
#define RCC_PREDIV1_Div1 ((uint32_t)0x00000000)
|
||||
#define RCC_PREDIV1_Div2 ((uint32_t)0x00000001)
|
||||
#define RCC_PREDIV1_Div3 ((uint32_t)0x00000002)
|
||||
#define RCC_PREDIV1_Div4 ((uint32_t)0x00000003)
|
||||
#define RCC_PREDIV1_Div5 ((uint32_t)0x00000004)
|
||||
#define RCC_PREDIV1_Div6 ((uint32_t)0x00000005)
|
||||
#define RCC_PREDIV1_Div7 ((uint32_t)0x00000006)
|
||||
#define RCC_PREDIV1_Div8 ((uint32_t)0x00000007)
|
||||
#define RCC_PREDIV1_Div9 ((uint32_t)0x00000008)
|
||||
#define RCC_PREDIV1_Div10 ((uint32_t)0x00000009)
|
||||
#define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A)
|
||||
#define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B)
|
||||
#define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C)
|
||||
#define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D)
|
||||
#define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E)
|
||||
#define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F)
|
||||
|
||||
#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PREDIV1_clock_source
|
||||
* @{
|
||||
*/
|
||||
#ifdef STM32F10X_CL
|
||||
/* PREDIV1 clock source (for STM32 connectivity line devices) */
|
||||
#define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
|
||||
#define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000)
|
||||
|
||||
#define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \
|
||||
((SOURCE) == RCC_PREDIV1_Source_PLL2))
|
||||
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
||||
/* PREDIV1 clock source (for STM32 Value line devices) */
|
||||
#define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
|
||||
|
||||
#define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE))
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef STM32F10X_CL
|
||||
/** @defgroup PREDIV2_division_factor
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_PREDIV2_Div1 ((uint32_t)0x00000000)
|
||||
#define RCC_PREDIV2_Div2 ((uint32_t)0x00000010)
|
||||
#define RCC_PREDIV2_Div3 ((uint32_t)0x00000020)
|
||||
#define RCC_PREDIV2_Div4 ((uint32_t)0x00000030)
|
||||
#define RCC_PREDIV2_Div5 ((uint32_t)0x00000040)
|
||||
#define RCC_PREDIV2_Div6 ((uint32_t)0x00000050)
|
||||
#define RCC_PREDIV2_Div7 ((uint32_t)0x00000060)
|
||||
#define RCC_PREDIV2_Div8 ((uint32_t)0x00000070)
|
||||
#define RCC_PREDIV2_Div9 ((uint32_t)0x00000080)
|
||||
#define RCC_PREDIV2_Div10 ((uint32_t)0x00000090)
|
||||
#define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0)
|
||||
#define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0)
|
||||
#define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0)
|
||||
#define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0)
|
||||
#define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0)
|
||||
#define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0)
|
||||
|
||||
#define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \
|
||||
((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \
|
||||
((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \
|
||||
((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \
|
||||
((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \
|
||||
((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \
|
||||
((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \
|
||||
((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PLL2_multiplication_factor
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_PLL2Mul_8 ((uint32_t)0x00000600)
|
||||
#define RCC_PLL2Mul_9 ((uint32_t)0x00000700)
|
||||
#define RCC_PLL2Mul_10 ((uint32_t)0x00000800)
|
||||
#define RCC_PLL2Mul_11 ((uint32_t)0x00000900)
|
||||
#define RCC_PLL2Mul_12 ((uint32_t)0x00000A00)
|
||||
#define RCC_PLL2Mul_13 ((uint32_t)0x00000B00)
|
||||
#define RCC_PLL2Mul_14 ((uint32_t)0x00000C00)
|
||||
#define RCC_PLL2Mul_16 ((uint32_t)0x00000E00)
|
||||
#define RCC_PLL2Mul_20 ((uint32_t)0x00000F00)
|
||||
|
||||
#define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \
|
||||
((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \
|
||||
((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \
|
||||
((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \
|
||||
((MUL) == RCC_PLL2Mul_20))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PLL3_multiplication_factor
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_PLL3Mul_8 ((uint32_t)0x00006000)
|
||||
#define RCC_PLL3Mul_9 ((uint32_t)0x00007000)
|
||||
#define RCC_PLL3Mul_10 ((uint32_t)0x00008000)
|
||||
#define RCC_PLL3Mul_11 ((uint32_t)0x00009000)
|
||||
#define RCC_PLL3Mul_12 ((uint32_t)0x0000A000)
|
||||
#define RCC_PLL3Mul_13 ((uint32_t)0x0000B000)
|
||||
#define RCC_PLL3Mul_14 ((uint32_t)0x0000C000)
|
||||
#define RCC_PLL3Mul_16 ((uint32_t)0x0000E000)
|
||||
#define RCC_PLL3Mul_20 ((uint32_t)0x0000F000)
|
||||
|
||||
#define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \
|
||||
((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \
|
||||
((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \
|
||||
((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \
|
||||
((MUL) == RCC_PLL3Mul_20))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32F10X_CL */
|
||||
|
||||
|
||||
/** @defgroup System_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
|
||||
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
|
||||
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_HSE) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AHB_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
|
||||
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
|
||||
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
|
||||
#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
|
||||
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
|
||||
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
|
||||
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
|
||||
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
|
||||
#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
|
||||
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
|
||||
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
|
||||
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
|
||||
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
|
||||
((HCLK) == RCC_SYSCLK_Div512))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup APB1_APB2_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
|
||||
#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
|
||||
#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
|
||||
#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
|
||||
#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
|
||||
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
|
||||
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
|
||||
((PCLK) == RCC_HCLK_Div16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Interrupt_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_IT_LSIRDY ((uint8_t)0x01)
|
||||
#define RCC_IT_LSERDY ((uint8_t)0x02)
|
||||
#define RCC_IT_HSIRDY ((uint8_t)0x04)
|
||||
#define RCC_IT_HSERDY ((uint8_t)0x08)
|
||||
#define RCC_IT_PLLRDY ((uint8_t)0x10)
|
||||
#define RCC_IT_CSS ((uint8_t)0x80)
|
||||
|
||||
#ifndef STM32F10X_CL
|
||||
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))
|
||||
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
|
||||
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
|
||||
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
|
||||
#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))
|
||||
#else
|
||||
#define RCC_IT_PLL2RDY ((uint8_t)0x20)
|
||||
#define RCC_IT_PLL3RDY ((uint8_t)0x40)
|
||||
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
|
||||
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
|
||||
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
|
||||
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
|
||||
((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY))
|
||||
#define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
|
||||
#endif /* STM32F10X_CL */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifndef STM32F10X_CL
|
||||
/** @defgroup USB_Device_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
|
||||
#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
|
||||
|
||||
#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
|
||||
((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#else
|
||||
/** @defgroup USB_OTG_FS_clock_source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00)
|
||||
#define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01)
|
||||
|
||||
#define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \
|
||||
((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F10X_CL */
|
||||
|
||||
|
||||
#ifdef STM32F10X_CL
|
||||
/** @defgroup I2S2_clock_source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
|
||||
#define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01)
|
||||
|
||||
#define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \
|
||||
((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S3_clock_source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00)
|
||||
#define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01)
|
||||
|
||||
#define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \
|
||||
((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F10X_CL */
|
||||
|
||||
|
||||
/** @defgroup ADC_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
|
||||
#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
|
||||
#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
|
||||
#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
|
||||
#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
|
||||
((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LSE_configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_LSE_OFF ((uint8_t)0x00)
|
||||
#define RCC_LSE_ON ((uint8_t)0x01)
|
||||
#define RCC_LSE_Bypass ((uint8_t)0x04)
|
||||
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
|
||||
((LSE) == RCC_LSE_Bypass))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
|
||||
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
|
||||
#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
|
||||
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_LSI) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AHB_peripheral
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
|
||||
#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
|
||||
#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
|
||||
#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
|
||||
#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
|
||||
|
||||
#ifndef STM32F10X_CL
|
||||
#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
|
||||
#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
|
||||
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
|
||||
#else
|
||||
#define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)
|
||||
#define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)
|
||||
#define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)
|
||||
#define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)
|
||||
|
||||
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00))
|
||||
#define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00))
|
||||
#endif /* STM32F10X_CL */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup APB2_peripheral
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
|
||||
#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
|
||||
#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
|
||||
#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
|
||||
#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
|
||||
#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
|
||||
#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
|
||||
#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
|
||||
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
|
||||
#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
|
||||
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
|
||||
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
|
||||
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
|
||||
#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
|
||||
#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
|
||||
#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000)
|
||||
#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000)
|
||||
#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000)
|
||||
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)
|
||||
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
|
||||
#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000)
|
||||
|
||||
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup APB1_peripheral
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
|
||||
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
|
||||
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
|
||||
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
|
||||
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
|
||||
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
|
||||
#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
|
||||
#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
|
||||
#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
|
||||
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
|
||||
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
|
||||
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
|
||||
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
|
||||
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
|
||||
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
|
||||
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
|
||||
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
|
||||
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
|
||||
#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
|
||||
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
|
||||
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
|
||||
#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
|
||||
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
|
||||
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
|
||||
#define RCC_APB1Periph_CEC ((uint32_t)0x40000000)
|
||||
|
||||
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Clock_source_to_output_on_MCO_pin
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_MCO_NoClock ((uint8_t)0x00)
|
||||
#define RCC_MCO_SYSCLK ((uint8_t)0x04)
|
||||
#define RCC_MCO_HSI ((uint8_t)0x05)
|
||||
#define RCC_MCO_HSE ((uint8_t)0x06)
|
||||
#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
|
||||
|
||||
#ifndef STM32F10X_CL
|
||||
#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
|
||||
((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
|
||||
((MCO) == RCC_MCO_PLLCLK_Div2))
|
||||
#else
|
||||
#define RCC_MCO_PLL2CLK ((uint8_t)0x08)
|
||||
#define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09)
|
||||
#define RCC_MCO_XT1 ((uint8_t)0x0A)
|
||||
#define RCC_MCO_PLL3CLK ((uint8_t)0x0B)
|
||||
|
||||
#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
|
||||
((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
|
||||
((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \
|
||||
((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \
|
||||
((MCO) == RCC_MCO_PLL3CLK))
|
||||
#endif /* STM32F10X_CL */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
|
||||
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
|
||||
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
|
||||
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
|
||||
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
|
||||
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
|
||||
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
|
||||
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
|
||||
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
|
||||
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
|
||||
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
|
||||
|
||||
#ifndef STM32F10X_CL
|
||||
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
|
||||
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
|
||||
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
|
||||
((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
|
||||
((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
|
||||
((FLAG) == RCC_FLAG_LPWRRST))
|
||||
#else
|
||||
#define RCC_FLAG_PLL2RDY ((uint8_t)0x3B)
|
||||
#define RCC_FLAG_PLL3RDY ((uint8_t)0x3D)
|
||||
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
|
||||
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
|
||||
((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \
|
||||
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
|
||||
((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
|
||||
((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
|
||||
((FLAG) == RCC_FLAG_LPWRRST))
|
||||
#endif /* STM32F10X_CL */
|
||||
|
||||
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void RCC_DeInit(void);
|
||||
void RCC_HSEConfig(uint32_t RCC_HSE);
|
||||
ErrorStatus RCC_WaitForHSEStartUp(void);
|
||||
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
|
||||
void RCC_HSICmd(FunctionalState NewState);
|
||||
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
|
||||
void RCC_PLLCmd(FunctionalState NewState);
|
||||
|
||||
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
|
||||
void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
|
||||
#endif
|
||||
|
||||
#ifdef STM32F10X_CL
|
||||
void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
|
||||
void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
|
||||
void RCC_PLL2Cmd(FunctionalState NewState);
|
||||
void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
|
||||
void RCC_PLL3Cmd(FunctionalState NewState);
|
||||
#endif /* STM32F10X_CL */
|
||||
|
||||
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
|
||||
uint8_t RCC_GetSYSCLKSource(void);
|
||||
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
|
||||
void RCC_PCLK1Config(uint32_t RCC_HCLK);
|
||||
void RCC_PCLK2Config(uint32_t RCC_HCLK);
|
||||
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
|
||||
|
||||
#ifndef STM32F10X_CL
|
||||
void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
|
||||
#else
|
||||
void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);
|
||||
#endif /* STM32F10X_CL */
|
||||
|
||||
void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
|
||||
|
||||
#ifdef STM32F10X_CL
|
||||
void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);
|
||||
void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
|
||||
#endif /* STM32F10X_CL */
|
||||
|
||||
void RCC_LSEConfig(uint8_t RCC_LSE);
|
||||
void RCC_LSICmd(FunctionalState NewState);
|
||||
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
|
||||
void RCC_RTCCLKCmd(FunctionalState NewState);
|
||||
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
|
||||
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
|
||||
#ifdef STM32F10X_CL
|
||||
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
|
||||
#endif /* STM32F10X_CL */
|
||||
|
||||
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
void RCC_BackupResetCmd(FunctionalState NewState);
|
||||
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
|
||||
void RCC_MCOConfig(uint8_t RCC_MCO);
|
||||
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
|
||||
void RCC_ClearFlag(void);
|
||||
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
|
||||
void RCC_ClearITPendingBit(uint8_t RCC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_RCC_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,339 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_rtc.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the RTC firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_rtc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC
|
||||
* @brief RTC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */
|
||||
#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified RTC interrupts.
|
||||
* @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_IT_OW: Overflow interrupt
|
||||
* @arg RTC_IT_ALR: Alarm interrupt
|
||||
* @arg RTC_IT_SEC: Second interrupt
|
||||
* @param NewState: new state of the specified RTC interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RTC_IT(RTC_IT));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
RTC->CRH |= RTC_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
RTC->CRH &= (uint16_t)~RTC_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters the RTC configuration mode.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void RTC_EnterConfigMode(void)
|
||||
{
|
||||
/* Set the CNF flag to enter in the Configuration Mode */
|
||||
RTC->CRL |= RTC_CRL_CNF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Exits from the RTC configuration mode.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void RTC_ExitConfigMode(void)
|
||||
{
|
||||
/* Reset the CNF flag to exit from the Configuration Mode */
|
||||
RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the RTC counter value.
|
||||
* @param None
|
||||
* @retval RTC counter value.
|
||||
*/
|
||||
uint32_t RTC_GetCounter(void)
|
||||
{
|
||||
uint16_t tmp = 0;
|
||||
tmp = RTC->CNTL;
|
||||
return (((uint32_t)RTC->CNTH << 16 ) | tmp) ;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the RTC counter value.
|
||||
* @param CounterValue: RTC counter new value.
|
||||
* @retval None
|
||||
*/
|
||||
void RTC_SetCounter(uint32_t CounterValue)
|
||||
{
|
||||
RTC_EnterConfigMode();
|
||||
/* Set RTC COUNTER MSB word */
|
||||
RTC->CNTH = CounterValue >> 16;
|
||||
/* Set RTC COUNTER LSB word */
|
||||
RTC->CNTL = (CounterValue & RTC_LSB_MASK);
|
||||
RTC_ExitConfigMode();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the RTC prescaler value.
|
||||
* @param PrescalerValue: RTC prescaler new value.
|
||||
* @retval None
|
||||
*/
|
||||
void RTC_SetPrescaler(uint32_t PrescalerValue)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RTC_PRESCALER(PrescalerValue));
|
||||
|
||||
RTC_EnterConfigMode();
|
||||
/* Set RTC PRESCALER MSB word */
|
||||
RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16;
|
||||
/* Set RTC PRESCALER LSB word */
|
||||
RTC->PRLL = (PrescalerValue & RTC_LSB_MASK);
|
||||
RTC_ExitConfigMode();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the RTC alarm value.
|
||||
* @param AlarmValue: RTC alarm new value.
|
||||
* @retval None
|
||||
*/
|
||||
void RTC_SetAlarm(uint32_t AlarmValue)
|
||||
{
|
||||
RTC_EnterConfigMode();
|
||||
/* Set the ALARM MSB word */
|
||||
RTC->ALRH = AlarmValue >> 16;
|
||||
/* Set the ALARM LSB word */
|
||||
RTC->ALRL = (AlarmValue & RTC_LSB_MASK);
|
||||
RTC_ExitConfigMode();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the RTC divider value.
|
||||
* @param None
|
||||
* @retval RTC Divider value.
|
||||
*/
|
||||
uint32_t RTC_GetDivider(void)
|
||||
{
|
||||
uint32_t tmp = 0x00;
|
||||
tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;
|
||||
tmp |= RTC->DIVL;
|
||||
return tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Waits until last write operation on RTC registers has finished.
|
||||
* @note This function must be called before any write to RTC registers.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void RTC_WaitForLastTask(void)
|
||||
{
|
||||
/* Loop until RTOFF flag is set */
|
||||
while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
|
||||
* are synchronized with RTC APB clock.
|
||||
* @note This function must be called before any read operation after an APB reset
|
||||
* or an APB clock stop.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void RTC_WaitForSynchro(void)
|
||||
{
|
||||
/* Clear RSF flag */
|
||||
RTC->CRL &= (uint16_t)~RTC_FLAG_RSF;
|
||||
/* Loop until RSF flag is set */
|
||||
while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified RTC flag is set or not.
|
||||
* @param RTC_FLAG: specifies the flag to check.
|
||||
* This parameter can be one the following values:
|
||||
* @arg RTC_FLAG_RTOFF: RTC Operation OFF flag
|
||||
* @arg RTC_FLAG_RSF: Registers Synchronized flag
|
||||
* @arg RTC_FLAG_OW: Overflow flag
|
||||
* @arg RTC_FLAG_ALR: Alarm flag
|
||||
* @arg RTC_FLAG_SEC: Second flag
|
||||
* @retval The new state of RTC_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
|
||||
|
||||
if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the RTC's pending flags.
|
||||
* @param RTC_FLAG: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after
|
||||
* an APB reset or an APB Clock stop.
|
||||
* @arg RTC_FLAG_OW: Overflow flag
|
||||
* @arg RTC_FLAG_ALR: Alarm flag
|
||||
* @arg RTC_FLAG_SEC: Second flag
|
||||
* @retval None
|
||||
*/
|
||||
void RTC_ClearFlag(uint16_t RTC_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
|
||||
|
||||
/* Clear the corresponding RTC flag */
|
||||
RTC->CRL &= (uint16_t)~RTC_FLAG;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified RTC interrupt has occurred or not.
|
||||
* @param RTC_IT: specifies the RTC interrupts sources to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RTC_IT_OW: Overflow interrupt
|
||||
* @arg RTC_IT_ALR: Alarm interrupt
|
||||
* @arg RTC_IT_SEC: Second interrupt
|
||||
* @retval The new state of the RTC_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus RTC_GetITStatus(uint16_t RTC_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RTC_GET_IT(RTC_IT));
|
||||
|
||||
bitstatus = (ITStatus)(RTC->CRL & RTC_IT);
|
||||
if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the RTC's interrupt pending bits.
|
||||
* @param RTC_IT: specifies the interrupt pending bit to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_IT_OW: Overflow interrupt
|
||||
* @arg RTC_IT_ALR: Alarm interrupt
|
||||
* @arg RTC_IT_SEC: Second interrupt
|
||||
* @retval None
|
||||
*/
|
||||
void RTC_ClearITPendingBit(uint16_t RTC_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RTC_IT(RTC_IT));
|
||||
|
||||
/* Clear the corresponding RTC pending bit */
|
||||
RTC->CRL &= (uint16_t)~RTC_IT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,135 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_rtc.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the RTC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_RTC_H
|
||||
#define __STM32F10x_RTC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_interrupts_define
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */
|
||||
#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */
|
||||
#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */
|
||||
#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))
|
||||
#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \
|
||||
((IT) == RTC_IT_SEC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_interrupts_flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */
|
||||
#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */
|
||||
#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */
|
||||
#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */
|
||||
#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */
|
||||
#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))
|
||||
#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \
|
||||
((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \
|
||||
((FLAG) == RTC_FLAG_SEC))
|
||||
#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
|
||||
void RTC_EnterConfigMode(void);
|
||||
void RTC_ExitConfigMode(void);
|
||||
uint32_t RTC_GetCounter(void);
|
||||
void RTC_SetCounter(uint32_t CounterValue);
|
||||
void RTC_SetPrescaler(uint32_t PrescalerValue);
|
||||
void RTC_SetAlarm(uint32_t AlarmValue);
|
||||
uint32_t RTC_GetDivider(void);
|
||||
void RTC_WaitForLastTask(void);
|
||||
void RTC_WaitForSynchro(void);
|
||||
FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
|
||||
void RTC_ClearFlag(uint16_t RTC_FLAG);
|
||||
ITStatus RTC_GetITStatus(uint16_t RTC_IT);
|
||||
void RTC_ClearITPendingBit(uint16_t RTC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_RTC_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,799 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_sdio.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the SDIO firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_sdio.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO
|
||||
* @brief SDIO driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ------------ SDIO registers bit address in the alias region ----------- */
|
||||
#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
|
||||
|
||||
/* --- CLKCR Register ---*/
|
||||
|
||||
/* Alias word address of CLKEN bit */
|
||||
#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
|
||||
#define CLKEN_BitNumber 0x08
|
||||
#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
|
||||
|
||||
/* --- CMD Register ---*/
|
||||
|
||||
/* Alias word address of SDIOSUSPEND bit */
|
||||
#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
|
||||
#define SDIOSUSPEND_BitNumber 0x0B
|
||||
#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
|
||||
|
||||
/* Alias word address of ENCMDCOMPL bit */
|
||||
#define ENCMDCOMPL_BitNumber 0x0C
|
||||
#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
|
||||
|
||||
/* Alias word address of NIEN bit */
|
||||
#define NIEN_BitNumber 0x0D
|
||||
#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
|
||||
|
||||
/* Alias word address of ATACMD bit */
|
||||
#define ATACMD_BitNumber 0x0E
|
||||
#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
|
||||
|
||||
/* --- DCTRL Register ---*/
|
||||
|
||||
/* Alias word address of DMAEN bit */
|
||||
#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
|
||||
#define DMAEN_BitNumber 0x03
|
||||
#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
|
||||
|
||||
/* Alias word address of RWSTART bit */
|
||||
#define RWSTART_BitNumber 0x08
|
||||
#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
|
||||
|
||||
/* Alias word address of RWSTOP bit */
|
||||
#define RWSTOP_BitNumber 0x09
|
||||
#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
|
||||
|
||||
/* Alias word address of RWMOD bit */
|
||||
#define RWMOD_BitNumber 0x0A
|
||||
#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
|
||||
|
||||
/* Alias word address of SDIOEN bit */
|
||||
#define SDIOEN_BitNumber 0x0B
|
||||
#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
|
||||
|
||||
/* ---------------------- SDIO registers bit mask ------------------------ */
|
||||
|
||||
/* --- CLKCR Register ---*/
|
||||
|
||||
/* CLKCR register clear mask */
|
||||
#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
|
||||
|
||||
/* --- PWRCTRL Register ---*/
|
||||
|
||||
/* SDIO PWRCTRL Mask */
|
||||
#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
|
||||
|
||||
/* --- DCTRL Register ---*/
|
||||
|
||||
/* SDIO DCTRL Clear Mask */
|
||||
#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
|
||||
|
||||
/* --- CMD Register ---*/
|
||||
|
||||
/* CMD Register clear mask */
|
||||
#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
|
||||
|
||||
/* SDIO RESP Registers Address */
|
||||
#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the SDIO peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_DeInit(void)
|
||||
{
|
||||
SDIO->POWER = 0x00000000;
|
||||
SDIO->CLKCR = 0x00000000;
|
||||
SDIO->ARG = 0x00000000;
|
||||
SDIO->CMD = 0x00000000;
|
||||
SDIO->DTIMER = 0x00000000;
|
||||
SDIO->DLEN = 0x00000000;
|
||||
SDIO->DCTRL = 0x00000000;
|
||||
SDIO->ICR = 0x00C007FF;
|
||||
SDIO->MASK = 0x00000000;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the SDIO peripheral according to the specified
|
||||
* parameters in the SDIO_InitStruct.
|
||||
* @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
|
||||
* that contains the configuration information for the SDIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
|
||||
assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
|
||||
assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
|
||||
assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
|
||||
assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl));
|
||||
|
||||
/*---------------------------- SDIO CLKCR Configuration ------------------------*/
|
||||
/* Get the SDIO CLKCR value */
|
||||
tmpreg = SDIO->CLKCR;
|
||||
|
||||
/* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
|
||||
tmpreg &= CLKCR_CLEAR_MASK;
|
||||
|
||||
/* Set CLKDIV bits according to SDIO_ClockDiv value */
|
||||
/* Set PWRSAV bit according to SDIO_ClockPowerSave value */
|
||||
/* Set BYPASS bit according to SDIO_ClockBypass value */
|
||||
/* Set WIDBUS bits according to SDIO_BusWide value */
|
||||
/* Set NEGEDGE bits according to SDIO_ClockEdge value */
|
||||
/* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
|
||||
tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
|
||||
SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
|
||||
SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
|
||||
|
||||
/* Write to SDIO CLKCR */
|
||||
SDIO->CLKCR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each SDIO_InitStruct member with its default value.
|
||||
* @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
|
||||
* will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
|
||||
{
|
||||
/* SDIO_InitStruct members default value */
|
||||
SDIO_InitStruct->SDIO_ClockDiv = 0x00;
|
||||
SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
|
||||
SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
|
||||
SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
|
||||
SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
|
||||
SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SDIO Clock.
|
||||
* @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_ClockCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the power status of the controller.
|
||||
* @param SDIO_PowerState: new state of the Power state.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDIO_PowerState_OFF
|
||||
* @arg SDIO_PowerState_ON
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_SetPowerState(uint32_t SDIO_PowerState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
|
||||
|
||||
SDIO->POWER &= PWR_PWRCTRL_MASK;
|
||||
SDIO->POWER |= SDIO_PowerState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the power status of the controller.
|
||||
* @param None
|
||||
* @retval Power status of the controller. The returned value can
|
||||
* be one of the following:
|
||||
* - 0x00: Power OFF
|
||||
* - 0x02: Power UP
|
||||
* - 0x03: Power ON
|
||||
*/
|
||||
uint32_t SDIO_GetPowerState(void)
|
||||
{
|
||||
return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SDIO interrupts.
|
||||
* @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
|
||||
* bus mode interrupt
|
||||
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
||||
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
||||
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
||||
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
||||
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
|
||||
* @param NewState: new state of the specified SDIO interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_IT(SDIO_IT));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the SDIO interrupts */
|
||||
SDIO->MASK |= SDIO_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the SDIO interrupts */
|
||||
SDIO->MASK &= ~SDIO_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SDIO DMA request.
|
||||
* @param NewState: new state of the selected SDIO DMA request.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_DMACmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the SDIO Command according to the specified
|
||||
* parameters in the SDIO_CmdInitStruct and send the command.
|
||||
* @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef
|
||||
* structure that contains the configuration information for the SDIO command.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
|
||||
assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
|
||||
assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
|
||||
assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
|
||||
|
||||
/*---------------------------- SDIO ARG Configuration ------------------------*/
|
||||
/* Set the SDIO Argument value */
|
||||
SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
|
||||
|
||||
/*---------------------------- SDIO CMD Configuration ------------------------*/
|
||||
/* Get the SDIO CMD value */
|
||||
tmpreg = SDIO->CMD;
|
||||
/* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
|
||||
tmpreg &= CMD_CLEAR_MASK;
|
||||
/* Set CMDINDEX bits according to SDIO_CmdIndex value */
|
||||
/* Set WAITRESP bits according to SDIO_Response value */
|
||||
/* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
|
||||
/* Set CPSMEN bits according to SDIO_CPSM value */
|
||||
tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
|
||||
| SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
|
||||
|
||||
/* Write to SDIO CMD */
|
||||
SDIO->CMD = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each SDIO_CmdInitStruct member with its default value.
|
||||
* @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
|
||||
* structure which will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
|
||||
{
|
||||
/* SDIO_CmdInitStruct members default value */
|
||||
SDIO_CmdInitStruct->SDIO_Argument = 0x00;
|
||||
SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
|
||||
SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
|
||||
SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
|
||||
SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns command index of last command for which response received.
|
||||
* @param None
|
||||
* @retval Returns the command index of the last command response received.
|
||||
*/
|
||||
uint8_t SDIO_GetCommandResponse(void)
|
||||
{
|
||||
return (uint8_t)(SDIO->RESPCMD);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns response received from the card for the last command.
|
||||
* @param SDIO_RESP: Specifies the SDIO response register.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDIO_RESP1: Response Register 1
|
||||
* @arg SDIO_RESP2: Response Register 2
|
||||
* @arg SDIO_RESP3: Response Register 3
|
||||
* @arg SDIO_RESP4: Response Register 4
|
||||
* @retval The Corresponding response register value.
|
||||
*/
|
||||
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_RESP(SDIO_RESP));
|
||||
|
||||
tmp = SDIO_RESP_ADDR + SDIO_RESP;
|
||||
|
||||
return (*(__IO uint32_t *) tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the SDIO data path according to the specified
|
||||
* parameters in the SDIO_DataInitStruct.
|
||||
* @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that
|
||||
* contains the configuration information for the SDIO command.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
|
||||
assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
|
||||
assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
|
||||
assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
|
||||
assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
|
||||
|
||||
/*---------------------------- SDIO DTIMER Configuration ---------------------*/
|
||||
/* Set the SDIO Data TimeOut value */
|
||||
SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
|
||||
|
||||
/*---------------------------- SDIO DLEN Configuration -----------------------*/
|
||||
/* Set the SDIO DataLength value */
|
||||
SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
|
||||
|
||||
/*---------------------------- SDIO DCTRL Configuration ----------------------*/
|
||||
/* Get the SDIO DCTRL value */
|
||||
tmpreg = SDIO->DCTRL;
|
||||
/* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
|
||||
tmpreg &= DCTRL_CLEAR_MASK;
|
||||
/* Set DEN bit according to SDIO_DPSM value */
|
||||
/* Set DTMODE bit according to SDIO_TransferMode value */
|
||||
/* Set DTDIR bit according to SDIO_TransferDir value */
|
||||
/* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
|
||||
tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
|
||||
| SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
|
||||
|
||||
/* Write to SDIO DCTRL */
|
||||
SDIO->DCTRL = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each SDIO_DataInitStruct member with its default value.
|
||||
* @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which
|
||||
* will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
|
||||
{
|
||||
/* SDIO_DataInitStruct members default value */
|
||||
SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
|
||||
SDIO_DataInitStruct->SDIO_DataLength = 0x00;
|
||||
SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
|
||||
SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
|
||||
SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
|
||||
SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns number of remaining data bytes to be transferred.
|
||||
* @param None
|
||||
* @retval Number of remaining data bytes to be transferred
|
||||
*/
|
||||
uint32_t SDIO_GetDataCounter(void)
|
||||
{
|
||||
return SDIO->DCOUNT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read one data word from Rx FIFO.
|
||||
* @param None
|
||||
* @retval Data received
|
||||
*/
|
||||
uint32_t SDIO_ReadData(void)
|
||||
{
|
||||
return SDIO->FIFO;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write one data word to Tx FIFO.
|
||||
* @param Data: 32-bit data word to write.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_WriteData(uint32_t Data)
|
||||
{
|
||||
SDIO->FIFO = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the number of words left to be written to or read from FIFO.
|
||||
* @param None
|
||||
* @retval Remaining number of words.
|
||||
*/
|
||||
uint32_t SDIO_GetFIFOCount(void)
|
||||
{
|
||||
return SDIO->FIFOCNT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Starts the SD I/O Read Wait operation.
|
||||
* @param NewState: new state of the Start SDIO Read Wait operation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_StartSDIOReadWait(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stops the SD I/O Read Wait operation.
|
||||
* @param NewState: new state of the Stop SDIO Read Wait operation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_StopSDIOReadWait(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets one of the two options of inserting read wait interval.
|
||||
* @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
|
||||
* This parameter can be:
|
||||
* @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
|
||||
* @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
|
||||
|
||||
*(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SD I/O Mode Operation.
|
||||
* @param NewState: new state of SDIO specific operation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_SetSDIOOperation(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SD I/O Mode suspend command sending.
|
||||
* @param NewState: new state of the SD I/O Mode suspend command.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the command completion signal.
|
||||
* @param NewState: new state of command completion signal.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_CommandCompletionCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the CE-ATA interrupt.
|
||||
* @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_CEATAITCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sends CE-ATA command (CMD61).
|
||||
* @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_SendCEATACmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified SDIO flag is set or not.
|
||||
* @param SDIO_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
||||
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
||||
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
|
||||
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
|
||||
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
|
||||
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
|
||||
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
|
||||
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
|
||||
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
||||
* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
|
||||
* bus mode.
|
||||
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
||||
* @arg SDIO_FLAG_CMDACT: Command transfer in progress
|
||||
* @arg SDIO_FLAG_TXACT: Data transmit in progress
|
||||
* @arg SDIO_FLAG_RXACT: Data receive in progress
|
||||
* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
|
||||
* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
|
||||
* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
|
||||
* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
|
||||
* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
|
||||
* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
|
||||
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
|
||||
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
|
||||
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
|
||||
* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
|
||||
* @retval The new state of SDIO_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_FLAG(SDIO_FLAG));
|
||||
|
||||
if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the SDIO's pending flags.
|
||||
* @param SDIO_FLAG: specifies the flag to clear.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
||||
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
||||
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
|
||||
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
|
||||
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
|
||||
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
|
||||
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
|
||||
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
|
||||
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
||||
* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
|
||||
* bus mode
|
||||
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
||||
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
|
||||
* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_ClearFlag(uint32_t SDIO_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
|
||||
|
||||
SDIO->ICR = SDIO_FLAG;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified SDIO interrupt has occurred or not.
|
||||
* @param SDIO_IT: specifies the SDIO interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
|
||||
* bus mode interrupt
|
||||
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
||||
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
||||
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
||||
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
||||
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
|
||||
* @retval The new state of SDIO_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_GET_IT(SDIO_IT));
|
||||
if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the SDIO's interrupt pending bits.
|
||||
* @param SDIO_IT: specifies the interrupt pending bit to clear.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
|
||||
* bus mode interrupt
|
||||
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
|
||||
|
||||
SDIO->ICR = SDIO_IT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,531 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_sdio.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the SDIO firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_SDIO_H
|
||||
#define __STM32F10x_SDIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
|
||||
This parameter can be a value of @ref SDIO_Clock_Edge */
|
||||
|
||||
uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
|
||||
enabled or disabled.
|
||||
This parameter can be a value of @ref SDIO_Clock_Bypass */
|
||||
|
||||
uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
|
||||
disabled when the bus is idle.
|
||||
This parameter can be a value of @ref SDIO_Clock_Power_Save */
|
||||
|
||||
uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.
|
||||
This parameter can be a value of @ref SDIO_Bus_Wide */
|
||||
|
||||
uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
|
||||
This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
|
||||
|
||||
uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
|
||||
This parameter can be a value between 0x00 and 0xFF. */
|
||||
|
||||
} SDIO_InitTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent
|
||||
to a card as part of a command message. If a command
|
||||
contains an argument, it must be loaded into this register
|
||||
before writing the command to the command register */
|
||||
|
||||
uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */
|
||||
|
||||
uint32_t SDIO_Response; /*!< Specifies the SDIO response type.
|
||||
This parameter can be a value of @ref SDIO_Response_Type */
|
||||
|
||||
uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
|
||||
This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
|
||||
|
||||
uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
|
||||
is enabled or disabled.
|
||||
This parameter can be a value of @ref SDIO_CPSM_State */
|
||||
} SDIO_CmdInitTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
|
||||
|
||||
uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */
|
||||
|
||||
uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.
|
||||
This parameter can be a value of @ref SDIO_Data_Block_Size */
|
||||
|
||||
uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer
|
||||
is a read or write.
|
||||
This parameter can be a value of @ref SDIO_Transfer_Direction */
|
||||
|
||||
uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
|
||||
This parameter can be a value of @ref SDIO_Transfer_Type */
|
||||
|
||||
uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
|
||||
is enabled or disabled.
|
||||
This parameter can be a value of @ref SDIO_DPSM_State */
|
||||
} SDIO_DataInitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Clock_Edge
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
|
||||
#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
|
||||
#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
|
||||
((EDGE) == SDIO_ClockEdge_Falling))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Clock_Bypass
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
|
||||
#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
|
||||
#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
|
||||
((BYPASS) == SDIO_ClockBypass_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Clock_Power_Save
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
|
||||
#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
|
||||
#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
|
||||
((SAVE) == SDIO_ClockPowerSave_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Bus_Wide
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_BusWide_1b ((uint32_t)0x00000000)
|
||||
#define SDIO_BusWide_4b ((uint32_t)0x00000800)
|
||||
#define SDIO_BusWide_8b ((uint32_t)0x00001000)
|
||||
#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
|
||||
((WIDE) == SDIO_BusWide_8b))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Hardware_Flow_Control
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
|
||||
#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
|
||||
#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
|
||||
((CONTROL) == SDIO_HardwareFlowControl_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Power_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_PowerState_OFF ((uint32_t)0x00000000)
|
||||
#define SDIO_PowerState_ON ((uint32_t)0x00000003)
|
||||
#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SDIO_Interrupt_sources
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
|
||||
#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
|
||||
#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
|
||||
#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
|
||||
#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
|
||||
#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
|
||||
#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
|
||||
#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
|
||||
#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
|
||||
#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
|
||||
#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
|
||||
#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
|
||||
#define SDIO_IT_TXACT ((uint32_t)0x00001000)
|
||||
#define SDIO_IT_RXACT ((uint32_t)0x00002000)
|
||||
#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
|
||||
#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
|
||||
#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
|
||||
#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
|
||||
#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
|
||||
#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
|
||||
#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
|
||||
#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
|
||||
#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
|
||||
#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
|
||||
#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Command_Index
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Response_Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_Response_No ((uint32_t)0x00000000)
|
||||
#define SDIO_Response_Short ((uint32_t)0x00000040)
|
||||
#define SDIO_Response_Long ((uint32_t)0x000000C0)
|
||||
#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
|
||||
((RESPONSE) == SDIO_Response_Short) || \
|
||||
((RESPONSE) == SDIO_Response_Long))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Wait_Interrupt_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
|
||||
#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
|
||||
#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
|
||||
#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
|
||||
((WAIT) == SDIO_Wait_Pend))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_CPSM_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_CPSM_Disable ((uint32_t)0x00000000)
|
||||
#define SDIO_CPSM_Enable ((uint32_t)0x00000400)
|
||||
#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Response_Registers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_RESP1 ((uint32_t)0x00000000)
|
||||
#define SDIO_RESP2 ((uint32_t)0x00000004)
|
||||
#define SDIO_RESP3 ((uint32_t)0x00000008)
|
||||
#define SDIO_RESP4 ((uint32_t)0x0000000C)
|
||||
#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
|
||||
((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Data_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Data_Block_Size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
|
||||
#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
|
||||
#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
|
||||
#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
|
||||
#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
|
||||
#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
|
||||
#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
|
||||
#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
|
||||
#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
|
||||
#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
|
||||
#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
|
||||
#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
|
||||
#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
|
||||
#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
|
||||
#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
|
||||
#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_2b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_4b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_8b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_16b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_32b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_64b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_128b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_256b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_512b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_1024b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_2048b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_4096b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_8192b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_16384b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Transfer_Direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
|
||||
#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
|
||||
#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
|
||||
((DIR) == SDIO_TransferDir_ToSDIO))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Transfer_Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_TransferMode_Block ((uint32_t)0x00000000)
|
||||
#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)
|
||||
#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
|
||||
((MODE) == SDIO_TransferMode_Block))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_DPSM_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_DPSM_Disable ((uint32_t)0x00000000)
|
||||
#define SDIO_DPSM_Enable ((uint32_t)0x00000001)
|
||||
#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
|
||||
#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
|
||||
#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
|
||||
#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
|
||||
#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
|
||||
#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
|
||||
#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
|
||||
#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
|
||||
#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
|
||||
#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
|
||||
#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
|
||||
#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
|
||||
#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
|
||||
#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
|
||||
#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
|
||||
#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
|
||||
#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
|
||||
#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
|
||||
#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
|
||||
#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
|
||||
#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
|
||||
#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
|
||||
#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
|
||||
#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
|
||||
#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
|
||||
((FLAG) == SDIO_FLAG_DCRCFAIL) || \
|
||||
((FLAG) == SDIO_FLAG_CTIMEOUT) || \
|
||||
((FLAG) == SDIO_FLAG_DTIMEOUT) || \
|
||||
((FLAG) == SDIO_FLAG_TXUNDERR) || \
|
||||
((FLAG) == SDIO_FLAG_RXOVERR) || \
|
||||
((FLAG) == SDIO_FLAG_CMDREND) || \
|
||||
((FLAG) == SDIO_FLAG_CMDSENT) || \
|
||||
((FLAG) == SDIO_FLAG_DATAEND) || \
|
||||
((FLAG) == SDIO_FLAG_STBITERR) || \
|
||||
((FLAG) == SDIO_FLAG_DBCKEND) || \
|
||||
((FLAG) == SDIO_FLAG_CMDACT) || \
|
||||
((FLAG) == SDIO_FLAG_TXACT) || \
|
||||
((FLAG) == SDIO_FLAG_RXACT) || \
|
||||
((FLAG) == SDIO_FLAG_TXFIFOHE) || \
|
||||
((FLAG) == SDIO_FLAG_RXFIFOHF) || \
|
||||
((FLAG) == SDIO_FLAG_TXFIFOF) || \
|
||||
((FLAG) == SDIO_FLAG_RXFIFOF) || \
|
||||
((FLAG) == SDIO_FLAG_TXFIFOE) || \
|
||||
((FLAG) == SDIO_FLAG_RXFIFOE) || \
|
||||
((FLAG) == SDIO_FLAG_TXDAVL) || \
|
||||
((FLAG) == SDIO_FLAG_RXDAVL) || \
|
||||
((FLAG) == SDIO_FLAG_SDIOIT) || \
|
||||
((FLAG) == SDIO_FLAG_CEATAEND))
|
||||
|
||||
#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
|
||||
|
||||
#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
|
||||
((IT) == SDIO_IT_DCRCFAIL) || \
|
||||
((IT) == SDIO_IT_CTIMEOUT) || \
|
||||
((IT) == SDIO_IT_DTIMEOUT) || \
|
||||
((IT) == SDIO_IT_TXUNDERR) || \
|
||||
((IT) == SDIO_IT_RXOVERR) || \
|
||||
((IT) == SDIO_IT_CMDREND) || \
|
||||
((IT) == SDIO_IT_CMDSENT) || \
|
||||
((IT) == SDIO_IT_DATAEND) || \
|
||||
((IT) == SDIO_IT_STBITERR) || \
|
||||
((IT) == SDIO_IT_DBCKEND) || \
|
||||
((IT) == SDIO_IT_CMDACT) || \
|
||||
((IT) == SDIO_IT_TXACT) || \
|
||||
((IT) == SDIO_IT_RXACT) || \
|
||||
((IT) == SDIO_IT_TXFIFOHE) || \
|
||||
((IT) == SDIO_IT_RXFIFOHF) || \
|
||||
((IT) == SDIO_IT_TXFIFOF) || \
|
||||
((IT) == SDIO_IT_RXFIFOF) || \
|
||||
((IT) == SDIO_IT_TXFIFOE) || \
|
||||
((IT) == SDIO_IT_RXFIFOE) || \
|
||||
((IT) == SDIO_IT_TXDAVL) || \
|
||||
((IT) == SDIO_IT_RXDAVL) || \
|
||||
((IT) == SDIO_IT_SDIOIT) || \
|
||||
((IT) == SDIO_IT_CEATAEND))
|
||||
|
||||
#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Read_Wait_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)
|
||||
#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)
|
||||
#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
|
||||
((MODE) == SDIO_ReadWaitMode_DATA2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void SDIO_DeInit(void);
|
||||
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
|
||||
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
|
||||
void SDIO_ClockCmd(FunctionalState NewState);
|
||||
void SDIO_SetPowerState(uint32_t SDIO_PowerState);
|
||||
uint32_t SDIO_GetPowerState(void);
|
||||
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
|
||||
void SDIO_DMACmd(FunctionalState NewState);
|
||||
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
|
||||
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
|
||||
uint8_t SDIO_GetCommandResponse(void);
|
||||
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
|
||||
void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
|
||||
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
|
||||
uint32_t SDIO_GetDataCounter(void);
|
||||
uint32_t SDIO_ReadData(void);
|
||||
void SDIO_WriteData(uint32_t Data);
|
||||
uint32_t SDIO_GetFIFOCount(void);
|
||||
void SDIO_StartSDIOReadWait(FunctionalState NewState);
|
||||
void SDIO_StopSDIOReadWait(FunctionalState NewState);
|
||||
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
|
||||
void SDIO_SetSDIOOperation(FunctionalState NewState);
|
||||
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
|
||||
void SDIO_CommandCompletionCmd(FunctionalState NewState);
|
||||
void SDIO_CEATAITCmd(FunctionalState NewState);
|
||||
void SDIO_SendCEATACmd(FunctionalState NewState);
|
||||
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
|
||||
void SDIO_ClearFlag(uint32_t SDIO_FLAG);
|
||||
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
|
||||
void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_SDIO_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,908 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_spi.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the SPI firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_spi.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SPI
|
||||
* @brief SPI driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SPI_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* SPI SPE mask */
|
||||
#define CR1_SPE_Set ((uint16_t)0x0040)
|
||||
#define CR1_SPE_Reset ((uint16_t)0xFFBF)
|
||||
|
||||
/* I2S I2SE mask */
|
||||
#define I2SCFGR_I2SE_Set ((uint16_t)0x0400)
|
||||
#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF)
|
||||
|
||||
/* SPI CRCNext mask */
|
||||
#define CR1_CRCNext_Set ((uint16_t)0x1000)
|
||||
|
||||
/* SPI CRCEN mask */
|
||||
#define CR1_CRCEN_Set ((uint16_t)0x2000)
|
||||
#define CR1_CRCEN_Reset ((uint16_t)0xDFFF)
|
||||
|
||||
/* SPI SSOE mask */
|
||||
#define CR2_SSOE_Set ((uint16_t)0x0004)
|
||||
#define CR2_SSOE_Reset ((uint16_t)0xFFFB)
|
||||
|
||||
/* SPI registers Masks */
|
||||
#define CR1_CLEAR_Mask ((uint16_t)0x3040)
|
||||
#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
|
||||
|
||||
/* SPI or I2S mode selection masks */
|
||||
#define SPI_Mode_Select ((uint16_t)0xF7FF)
|
||||
#define I2S_Mode_Select ((uint16_t)0x0800)
|
||||
|
||||
/* I2S clock source selection masks */
|
||||
#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000))
|
||||
#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000))
|
||||
#define I2S_MUL_MASK ((uint32_t)(0x0000F000))
|
||||
#define I2S_DIV_MASK ((uint32_t)(0x000000F0))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the SPIx peripheral registers to their default
|
||||
* reset values (Affects also the I2Ss).
|
||||
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
|
||||
if (SPIx == SPI1)
|
||||
{
|
||||
/* Enable SPI1 reset state */
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
|
||||
/* Release SPI1 from reset state */
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
|
||||
}
|
||||
else if (SPIx == SPI2)
|
||||
{
|
||||
/* Enable SPI2 reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
|
||||
/* Release SPI2 from reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (SPIx == SPI3)
|
||||
{
|
||||
/* Enable SPI3 reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
|
||||
/* Release SPI3 from reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the SPIx peripheral according to the specified
|
||||
* parameters in the SPI_InitStruct.
|
||||
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
|
||||
* contains the configuration information for the specified SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
|
||||
{
|
||||
uint16_t tmpreg = 0;
|
||||
|
||||
/* check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
|
||||
/* Check the SPI parameters */
|
||||
assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
|
||||
assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
|
||||
assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
|
||||
assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
|
||||
assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
|
||||
assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
|
||||
assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
|
||||
assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
|
||||
assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
|
||||
|
||||
/*---------------------------- SPIx CR1 Configuration ------------------------*/
|
||||
/* Get the SPIx CR1 value */
|
||||
tmpreg = SPIx->CR1;
|
||||
/* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
|
||||
tmpreg &= CR1_CLEAR_Mask;
|
||||
/* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
|
||||
master/salve mode, CPOL and CPHA */
|
||||
/* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
|
||||
/* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
|
||||
/* Set LSBFirst bit according to SPI_FirstBit value */
|
||||
/* Set BR bits according to SPI_BaudRatePrescaler value */
|
||||
/* Set CPOL bit according to SPI_CPOL value */
|
||||
/* Set CPHA bit according to SPI_CPHA value */
|
||||
tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
|
||||
SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
|
||||
SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
|
||||
SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
|
||||
/* Write to SPIx CR1 */
|
||||
SPIx->CR1 = tmpreg;
|
||||
|
||||
/* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
|
||||
SPIx->I2SCFGR &= SPI_Mode_Select;
|
||||
|
||||
/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
|
||||
/* Write to SPIx CRCPOLY */
|
||||
SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the SPIx peripheral according to the specified
|
||||
* parameters in the I2S_InitStruct.
|
||||
* @param SPIx: where x can be 2 or 3 to select the SPI peripheral
|
||||
* (configured in I2S mode).
|
||||
* @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
|
||||
* contains the configuration information for the specified SPI peripheral
|
||||
* configured in I2S mode.
|
||||
* @note
|
||||
* The function calculates the optimal prescaler needed to obtain the most
|
||||
* accurate audio frequency (depending on the I2S clock source, the PLL values
|
||||
* and the product configuration). But in case the prescaler value is greater
|
||||
* than 511, the default value (0x02) will be configured instead. *
|
||||
* @retval None
|
||||
*/
|
||||
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
|
||||
{
|
||||
uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
|
||||
uint32_t tmp = 0;
|
||||
RCC_ClocksTypeDef RCC_Clocks;
|
||||
uint32_t sourceclock = 0;
|
||||
|
||||
/* Check the I2S parameters */
|
||||
assert_param(IS_SPI_23_PERIPH(SPIx));
|
||||
assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
|
||||
assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
|
||||
assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
|
||||
assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
|
||||
assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
|
||||
assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
|
||||
|
||||
/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
|
||||
/* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
|
||||
SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
|
||||
SPIx->I2SPR = 0x0002;
|
||||
|
||||
/* Get the I2SCFGR register value */
|
||||
tmpreg = SPIx->I2SCFGR;
|
||||
|
||||
/* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
|
||||
if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
|
||||
{
|
||||
i2sodd = (uint16_t)0;
|
||||
i2sdiv = (uint16_t)2;
|
||||
}
|
||||
/* If the requested audio frequency is not the default, compute the prescaler */
|
||||
else
|
||||
{
|
||||
/* Check the frame length (For the Prescaler computing) */
|
||||
if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
|
||||
{
|
||||
/* Packet length is 16 bits */
|
||||
packetlength = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Packet length is 32 bits */
|
||||
packetlength = 2;
|
||||
}
|
||||
|
||||
/* Get the I2S clock source mask depending on the peripheral number */
|
||||
if(((uint32_t)SPIx) == SPI2_BASE)
|
||||
{
|
||||
/* The mask is relative to I2S2 */
|
||||
tmp = I2S2_CLOCK_SRC;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* The mask is relative to I2S3 */
|
||||
tmp = I2S3_CLOCK_SRC;
|
||||
}
|
||||
|
||||
/* Check the I2S clock source configuration depending on the Device:
|
||||
Only Connectivity line devices have the PLL3 VCO clock */
|
||||
#ifdef STM32F10X_CL
|
||||
if((RCC->CFGR2 & tmp) != 0)
|
||||
{
|
||||
/* Get the configuration bits of RCC PLL3 multiplier */
|
||||
tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12);
|
||||
|
||||
/* Get the value of the PLL3 multiplier */
|
||||
if((tmp > 5) && (tmp < 15))
|
||||
{
|
||||
/* Multiplier is between 8 and 14 (value 15 is forbidden) */
|
||||
tmp += 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (tmp == 15)
|
||||
{
|
||||
/* Multiplier is 20 */
|
||||
tmp = 20;
|
||||
}
|
||||
}
|
||||
/* Get the PREDIV2 value */
|
||||
sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1);
|
||||
|
||||
/* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */
|
||||
sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* I2S Clock source is System clock: Get System Clock frequency */
|
||||
RCC_GetClocksFreq(&RCC_Clocks);
|
||||
|
||||
/* Get the source clock value: based on System Clock value */
|
||||
sourceclock = RCC_Clocks.SYSCLK_Frequency;
|
||||
}
|
||||
#else /* STM32F10X_HD */
|
||||
/* I2S Clock source is System clock: Get System Clock frequency */
|
||||
RCC_GetClocksFreq(&RCC_Clocks);
|
||||
|
||||
/* Get the source clock value: based on System Clock value */
|
||||
sourceclock = RCC_Clocks.SYSCLK_Frequency;
|
||||
#endif /* STM32F10X_CL */
|
||||
|
||||
/* Compute the Real divider depending on the MCLK output state with a floating point */
|
||||
if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
|
||||
{
|
||||
/* MCLK output is enabled */
|
||||
tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* MCLK output is disabled */
|
||||
tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
|
||||
}
|
||||
|
||||
/* Remove the floating point */
|
||||
tmp = tmp / 10;
|
||||
|
||||
/* Check the parity of the divider */
|
||||
i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
|
||||
|
||||
/* Compute the i2sdiv prescaler */
|
||||
i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
|
||||
|
||||
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
|
||||
i2sodd = (uint16_t) (i2sodd << 8);
|
||||
}
|
||||
|
||||
/* Test if the divider is 1 or 0 or greater than 0xFF */
|
||||
if ((i2sdiv < 2) || (i2sdiv > 0xFF))
|
||||
{
|
||||
/* Set the default values */
|
||||
i2sdiv = 2;
|
||||
i2sodd = 0;
|
||||
}
|
||||
|
||||
/* Write to SPIx I2SPR register the computed value */
|
||||
SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
|
||||
|
||||
/* Configure the I2S with the SPI_InitStruct values */
|
||||
tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \
|
||||
(uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
|
||||
(uint16_t)I2S_InitStruct->I2S_CPOL))));
|
||||
|
||||
/* Write to SPIx I2SCFGR */
|
||||
SPIx->I2SCFGR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each SPI_InitStruct member with its default value.
|
||||
* @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
|
||||
{
|
||||
/*--------------- Reset SPI init structure parameters values -----------------*/
|
||||
/* Initialize the SPI_Direction member */
|
||||
SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
|
||||
/* initialize the SPI_Mode member */
|
||||
SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
|
||||
/* initialize the SPI_DataSize member */
|
||||
SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
|
||||
/* Initialize the SPI_CPOL member */
|
||||
SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
|
||||
/* Initialize the SPI_CPHA member */
|
||||
SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
|
||||
/* Initialize the SPI_NSS member */
|
||||
SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
|
||||
/* Initialize the SPI_BaudRatePrescaler member */
|
||||
SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
|
||||
/* Initialize the SPI_FirstBit member */
|
||||
SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
|
||||
/* Initialize the SPI_CRCPolynomial member */
|
||||
SPI_InitStruct->SPI_CRCPolynomial = 7;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each I2S_InitStruct member with its default value.
|
||||
* @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
|
||||
{
|
||||
/*--------------- Reset I2S init structure parameters values -----------------*/
|
||||
/* Initialize the I2S_Mode member */
|
||||
I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
|
||||
|
||||
/* Initialize the I2S_Standard member */
|
||||
I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
|
||||
|
||||
/* Initialize the I2S_DataFormat member */
|
||||
I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
|
||||
|
||||
/* Initialize the I2S_MCLKOutput member */
|
||||
I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
|
||||
|
||||
/* Initialize the I2S_AudioFreq member */
|
||||
I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
|
||||
|
||||
/* Initialize the I2S_CPOL member */
|
||||
I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified SPI peripheral.
|
||||
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @param NewState: new state of the SPIx peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected SPI peripheral */
|
||||
SPIx->CR1 |= CR1_SPE_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected SPI peripheral */
|
||||
SPIx->CR1 &= CR1_SPE_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified SPI peripheral (in I2S mode).
|
||||
* @param SPIx: where x can be 2 or 3 to select the SPI peripheral.
|
||||
* @param NewState: new state of the SPIx peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_23_PERIPH(SPIx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected SPI peripheral (in I2S mode) */
|
||||
SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected SPI peripheral (in I2S mode) */
|
||||
SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified SPI/I2S interrupts.
|
||||
* @param SPIx: where x can be
|
||||
* - 1, 2 or 3 in SPI mode
|
||||
* - 2 or 3 in I2S mode
|
||||
* @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
|
||||
* @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
|
||||
* @arg SPI_I2S_IT_ERR: Error interrupt mask
|
||||
* @param NewState: new state of the specified SPI/I2S interrupt.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
|
||||
{
|
||||
uint16_t itpos = 0, itmask = 0 ;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
|
||||
|
||||
/* Get the SPI/I2S IT index */
|
||||
itpos = SPI_I2S_IT >> 4;
|
||||
|
||||
/* Set the IT mask */
|
||||
itmask = (uint16_t)1 << (uint16_t)itpos;
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected SPI/I2S interrupt */
|
||||
SPIx->CR2 |= itmask;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected SPI/I2S interrupt */
|
||||
SPIx->CR2 &= (uint16_t)~itmask;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SPIx/I2Sx DMA interface.
|
||||
* @param SPIx: where x can be
|
||||
* - 1, 2 or 3 in SPI mode
|
||||
* - 2 or 3 in I2S mode
|
||||
* @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
|
||||
* @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
|
||||
* @param NewState: new state of the selected SPI/I2S DMA transfer request.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected SPI/I2S DMA requests */
|
||||
SPIx->CR2 |= SPI_I2S_DMAReq;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected SPI/I2S DMA requests */
|
||||
SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Transmits a Data through the SPIx/I2Sx peripheral.
|
||||
* @param SPIx: where x can be
|
||||
* - 1, 2 or 3 in SPI mode
|
||||
* - 2 or 3 in I2S mode
|
||||
* @param Data : Data to be transmitted.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
|
||||
/* Write in the DR register the data to be sent */
|
||||
SPIx->DR = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
|
||||
* @param SPIx: where x can be
|
||||
* - 1, 2 or 3 in SPI mode
|
||||
* - 2 or 3 in I2S mode
|
||||
* @retval The value of the received data.
|
||||
*/
|
||||
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
|
||||
/* Return the data in the DR register */
|
||||
return SPIx->DR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures internally by software the NSS pin for the selected SPI.
|
||||
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
|
||||
* @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
|
||||
if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
|
||||
{
|
||||
/* Set NSS pin internally by software */
|
||||
SPIx->CR1 |= SPI_NSSInternalSoft_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Reset NSS pin internally by software */
|
||||
SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SS output for the selected SPI.
|
||||
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @param NewState: new state of the SPIx SS output.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected SPI SS output */
|
||||
SPIx->CR2 |= CR2_SSOE_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected SPI SS output */
|
||||
SPIx->CR2 &= CR2_SSOE_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the data size for the selected SPI.
|
||||
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @param SPI_DataSize: specifies the SPI data size.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_DataSize_16b: Set data frame format to 16bit
|
||||
* @arg SPI_DataSize_8b: Set data frame format to 8bit
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_SPI_DATASIZE(SPI_DataSize));
|
||||
/* Clear DFF bit */
|
||||
SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
|
||||
/* Set new DFF bit value */
|
||||
SPIx->CR1 |= SPI_DataSize;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Transmit the SPIx CRC value.
|
||||
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_TransmitCRC(SPI_TypeDef* SPIx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
|
||||
/* Enable the selected SPI CRC transmission */
|
||||
SPIx->CR1 |= CR1_CRCNext_Set;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the CRC value calculation of the transferred bytes.
|
||||
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @param NewState: new state of the SPIx CRC value calculation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected SPI CRC calculation */
|
||||
SPIx->CR1 |= CR1_CRCEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected SPI CRC calculation */
|
||||
SPIx->CR1 &= CR1_CRCEN_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the transmit or the receive CRC register value for the specified SPI.
|
||||
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @param SPI_CRC: specifies the CRC register to be read.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_CRC_Tx: Selects Tx CRC register
|
||||
* @arg SPI_CRC_Rx: Selects Rx CRC register
|
||||
* @retval The selected CRC register value..
|
||||
*/
|
||||
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
|
||||
{
|
||||
uint16_t crcreg = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_SPI_CRC(SPI_CRC));
|
||||
if (SPI_CRC != SPI_CRC_Rx)
|
||||
{
|
||||
/* Get the Tx CRC register */
|
||||
crcreg = SPIx->TXCRCR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get the Rx CRC register */
|
||||
crcreg = SPIx->RXCRCR;
|
||||
}
|
||||
/* Return the selected CRC register */
|
||||
return crcreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the CRC Polynomial register value for the specified SPI.
|
||||
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @retval The CRC Polynomial register value.
|
||||
*/
|
||||
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
|
||||
/* Return the CRC polynomial register */
|
||||
return SPIx->CRCPR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the data transfer direction in bi-directional mode for the specified SPI.
|
||||
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @param SPI_Direction: specifies the data transfer direction in bi-directional mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_Direction_Tx: Selects Tx transmission direction
|
||||
* @arg SPI_Direction_Rx: Selects Rx receive direction
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_SPI_DIRECTION(SPI_Direction));
|
||||
if (SPI_Direction == SPI_Direction_Tx)
|
||||
{
|
||||
/* Set the Tx only mode */
|
||||
SPIx->CR1 |= SPI_Direction_Tx;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set the Rx only mode */
|
||||
SPIx->CR1 &= SPI_Direction_Rx;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified SPI/I2S flag is set or not.
|
||||
* @param SPIx: where x can be
|
||||
* - 1, 2 or 3 in SPI mode
|
||||
* - 2 or 3 in I2S mode
|
||||
* @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
|
||||
* @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
|
||||
* @arg SPI_I2S_FLAG_BSY: Busy flag.
|
||||
* @arg SPI_I2S_FLAG_OVR: Overrun flag.
|
||||
* @arg SPI_FLAG_MODF: Mode Fault flag.
|
||||
* @arg SPI_FLAG_CRCERR: CRC Error flag.
|
||||
* @arg I2S_FLAG_UDR: Underrun Error flag.
|
||||
* @arg I2S_FLAG_CHSIDE: Channel Side flag.
|
||||
* @retval The new state of SPI_I2S_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
|
||||
/* Check the status of the specified SPI/I2S flag */
|
||||
if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
|
||||
{
|
||||
/* SPI_I2S_FLAG is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* SPI_I2S_FLAG is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the SPI_I2S_FLAG status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the SPIx CRC Error (CRCERR) flag.
|
||||
* @param SPIx: where x can be
|
||||
* - 1, 2 or 3 in SPI mode
|
||||
* @param SPI_I2S_FLAG: specifies the SPI flag to clear.
|
||||
* This function clears only CRCERR flag.
|
||||
* @note
|
||||
* - OVR (OverRun error) flag is cleared by software sequence: a read
|
||||
* operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read
|
||||
* operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
|
||||
* - UDR (UnderRun error) flag is cleared by a read operation to
|
||||
* SPI_SR register (SPI_I2S_GetFlagStatus()).
|
||||
* - MODF (Mode Fault) flag is cleared by software sequence: a read/write
|
||||
* operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a
|
||||
* write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
|
||||
|
||||
/* Clear the selected SPI CRC Error (CRCERR) flag */
|
||||
SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
|
||||
* @param SPIx: where x can be
|
||||
* - 1, 2 or 3 in SPI mode
|
||||
* - 2 or 3 in I2S mode
|
||||
* @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
|
||||
* @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
|
||||
* @arg SPI_I2S_IT_OVR: Overrun interrupt.
|
||||
* @arg SPI_IT_MODF: Mode Fault interrupt.
|
||||
* @arg SPI_IT_CRCERR: CRC Error interrupt.
|
||||
* @arg I2S_IT_UDR: Underrun Error interrupt.
|
||||
* @retval The new state of SPI_I2S_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint16_t itpos = 0, itmask = 0, enablestatus = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
|
||||
|
||||
/* Get the SPI/I2S IT index */
|
||||
itpos = 0x01 << (SPI_I2S_IT & 0x0F);
|
||||
|
||||
/* Get the SPI/I2S IT mask */
|
||||
itmask = SPI_I2S_IT >> 4;
|
||||
|
||||
/* Set the IT mask */
|
||||
itmask = 0x01 << itmask;
|
||||
|
||||
/* Get the SPI_I2S_IT enable bit status */
|
||||
enablestatus = (SPIx->CR2 & itmask) ;
|
||||
|
||||
/* Check the status of the specified SPI/I2S interrupt */
|
||||
if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
|
||||
{
|
||||
/* SPI_I2S_IT is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* SPI_I2S_IT is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the SPI_I2S_IT status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
|
||||
* @param SPIx: where x can be
|
||||
* - 1, 2 or 3 in SPI mode
|
||||
* @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
|
||||
* This function clears only CRCERR interrupt pending bit.
|
||||
* @note
|
||||
* - OVR (OverRun Error) interrupt pending bit is cleared by software
|
||||
* sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData())
|
||||
* followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
|
||||
* - UDR (UnderRun Error) interrupt pending bit is cleared by a read
|
||||
* operation to SPI_SR register (SPI_I2S_GetITStatus()).
|
||||
* - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
|
||||
* a read/write operation to SPI_SR register (SPI_I2S_GetITStatus())
|
||||
* followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable
|
||||
* the SPI).
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
|
||||
{
|
||||
uint16_t itpos = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||
assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
|
||||
|
||||
/* Get the SPI IT index */
|
||||
itpos = 0x01 << (SPI_I2S_IT & 0x0F);
|
||||
|
||||
/* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
|
||||
SPIx->SR = (uint16_t)~itpos;
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,487 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_spi.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the SPI firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_SPI_H
|
||||
#define __STM32F10x_SPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SPI Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
|
||||
This parameter can be a value of @ref SPI_data_direction */
|
||||
|
||||
uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.
|
||||
This parameter can be a value of @ref SPI_mode */
|
||||
|
||||
uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
|
||||
This parameter can be a value of @ref SPI_data_size */
|
||||
|
||||
uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
|
||||
This parameter can be a value of @ref SPI_Clock_Polarity */
|
||||
|
||||
uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
|
||||
This parameter can be a value of @ref SPI_Clock_Phase */
|
||||
|
||||
uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
|
||||
hardware (NSS pin) or by software using the SSI bit.
|
||||
This parameter can be a value of @ref SPI_Slave_Select_management */
|
||||
|
||||
uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
|
||||
used to configure the transmit and receive SCK clock.
|
||||
This parameter can be a value of @ref SPI_BaudRate_Prescaler.
|
||||
@note The communication clock is derived from the master
|
||||
clock. The slave clock does not need to be set. */
|
||||
|
||||
uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
||||
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
|
||||
|
||||
uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
|
||||
}SPI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief I2S Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
|
||||
This parameter can be a value of @ref I2S_Mode */
|
||||
|
||||
uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Standard */
|
||||
|
||||
uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Data_Format */
|
||||
|
||||
uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
|
||||
This parameter can be a value of @ref I2S_MCLK_Output */
|
||||
|
||||
uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Audio_Frequency */
|
||||
|
||||
uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
|
||||
This parameter can be a value of @ref I2S_Clock_Polarity */
|
||||
}I2S_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
|
||||
((PERIPH) == SPI2) || \
|
||||
((PERIPH) == SPI3))
|
||||
|
||||
#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
|
||||
((PERIPH) == SPI3))
|
||||
|
||||
/** @defgroup SPI_data_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
|
||||
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
|
||||
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
|
||||
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
|
||||
#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
|
||||
((MODE) == SPI_Direction_2Lines_RxOnly) || \
|
||||
((MODE) == SPI_Direction_1Line_Rx) || \
|
||||
((MODE) == SPI_Direction_1Line_Tx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_Mode_Master ((uint16_t)0x0104)
|
||||
#define SPI_Mode_Slave ((uint16_t)0x0000)
|
||||
#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
|
||||
((MODE) == SPI_Mode_Slave))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_DataSize_16b ((uint16_t)0x0800)
|
||||
#define SPI_DataSize_8b ((uint16_t)0x0000)
|
||||
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
|
||||
((DATASIZE) == SPI_DataSize_8b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CPOL_Low ((uint16_t)0x0000)
|
||||
#define SPI_CPOL_High ((uint16_t)0x0002)
|
||||
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
|
||||
((CPOL) == SPI_CPOL_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Phase
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CPHA_1Edge ((uint16_t)0x0000)
|
||||
#define SPI_CPHA_2Edge ((uint16_t)0x0001)
|
||||
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
|
||||
((CPHA) == SPI_CPHA_2Edge))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Slave_Select_management
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_NSS_Soft ((uint16_t)0x0200)
|
||||
#define SPI_NSS_Hard ((uint16_t)0x0000)
|
||||
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
|
||||
((NSS) == SPI_NSS_Hard))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_BaudRate_Prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
|
||||
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
|
||||
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
|
||||
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
|
||||
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
|
||||
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
|
||||
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
|
||||
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
|
||||
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_4) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_8) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_16) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_32) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_64) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_128) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_256))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_MSB_LSB_transmission
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
|
||||
#define SPI_FirstBit_LSB ((uint16_t)0x0080)
|
||||
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
|
||||
((BIT) == SPI_FirstBit_LSB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
|
||||
#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
|
||||
#define I2S_Mode_MasterTx ((uint16_t)0x0200)
|
||||
#define I2S_Mode_MasterRx ((uint16_t)0x0300)
|
||||
#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
|
||||
((MODE) == I2S_Mode_SlaveRx) || \
|
||||
((MODE) == I2S_Mode_MasterTx) || \
|
||||
((MODE) == I2S_Mode_MasterRx) )
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Standard
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_Standard_Phillips ((uint16_t)0x0000)
|
||||
#define I2S_Standard_MSB ((uint16_t)0x0010)
|
||||
#define I2S_Standard_LSB ((uint16_t)0x0020)
|
||||
#define I2S_Standard_PCMShort ((uint16_t)0x0030)
|
||||
#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
|
||||
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
|
||||
((STANDARD) == I2S_Standard_MSB) || \
|
||||
((STANDARD) == I2S_Standard_LSB) || \
|
||||
((STANDARD) == I2S_Standard_PCMShort) || \
|
||||
((STANDARD) == I2S_Standard_PCMLong))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Data_Format
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_DataFormat_16b ((uint16_t)0x0000)
|
||||
#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
|
||||
#define I2S_DataFormat_24b ((uint16_t)0x0003)
|
||||
#define I2S_DataFormat_32b ((uint16_t)0x0005)
|
||||
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
|
||||
((FORMAT) == I2S_DataFormat_16bextended) || \
|
||||
((FORMAT) == I2S_DataFormat_24b) || \
|
||||
((FORMAT) == I2S_DataFormat_32b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_MCLK_Output
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
|
||||
#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
|
||||
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
|
||||
((OUTPUT) == I2S_MCLKOutput_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Audio_Frequency
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_AudioFreq_192k ((uint32_t)192000)
|
||||
#define I2S_AudioFreq_96k ((uint32_t)96000)
|
||||
#define I2S_AudioFreq_48k ((uint32_t)48000)
|
||||
#define I2S_AudioFreq_44k ((uint32_t)44100)
|
||||
#define I2S_AudioFreq_32k ((uint32_t)32000)
|
||||
#define I2S_AudioFreq_22k ((uint32_t)22050)
|
||||
#define I2S_AudioFreq_16k ((uint32_t)16000)
|
||||
#define I2S_AudioFreq_11k ((uint32_t)11025)
|
||||
#define I2S_AudioFreq_8k ((uint32_t)8000)
|
||||
#define I2S_AudioFreq_Default ((uint32_t)2)
|
||||
|
||||
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
|
||||
((FREQ) <= I2S_AudioFreq_192k)) || \
|
||||
((FREQ) == I2S_AudioFreq_Default))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_CPOL_Low ((uint16_t)0x0000)
|
||||
#define I2S_CPOL_High ((uint16_t)0x0008)
|
||||
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
|
||||
((CPOL) == I2S_CPOL_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_DMA_transfer_requests
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
|
||||
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
|
||||
#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_NSS_internal_software_management
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
|
||||
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
|
||||
#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
|
||||
((INTERNAL) == SPI_NSSInternalSoft_Reset))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_Transmit_Receive
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CRC_Tx ((uint8_t)0x00)
|
||||
#define SPI_CRC_Rx ((uint8_t)0x01)
|
||||
#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_direction_transmit_receive
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_Direction_Rx ((uint16_t)0xBFFF)
|
||||
#define SPI_Direction_Tx ((uint16_t)0x4000)
|
||||
#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
|
||||
((DIRECTION) == SPI_Direction_Tx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_IT_TXE ((uint8_t)0x71)
|
||||
#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
|
||||
#define SPI_I2S_IT_ERR ((uint8_t)0x50)
|
||||
#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
|
||||
((IT) == SPI_I2S_IT_RXNE) || \
|
||||
((IT) == SPI_I2S_IT_ERR))
|
||||
#define SPI_I2S_IT_OVR ((uint8_t)0x56)
|
||||
#define SPI_IT_MODF ((uint8_t)0x55)
|
||||
#define SPI_IT_CRCERR ((uint8_t)0x54)
|
||||
#define I2S_IT_UDR ((uint8_t)0x53)
|
||||
#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
|
||||
#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
|
||||
((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \
|
||||
((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
|
||||
#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
|
||||
#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
|
||||
#define I2S_FLAG_UDR ((uint16_t)0x0008)
|
||||
#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
|
||||
#define SPI_FLAG_MODF ((uint16_t)0x0020)
|
||||
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
|
||||
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
|
||||
#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
|
||||
#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
|
||||
((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
|
||||
((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
|
||||
((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_polynomial
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
|
||||
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
|
||||
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
|
||||
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
|
||||
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
|
||||
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
|
||||
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
|
||||
void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
|
||||
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
|
||||
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
|
||||
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
|
||||
void SPI_TransmitCRC(SPI_TypeDef* SPIx);
|
||||
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
|
||||
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
|
||||
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
|
||||
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
|
||||
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
|
||||
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
|
||||
void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F10x_SPI_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,412 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_usart.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the USART
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_USART_H
|
||||
#define __STM32F10x_USART_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USART
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief USART Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
|
||||
The baud rate is computed using the following formula:
|
||||
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
|
||||
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
|
||||
|
||||
uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref USART_Word_Length */
|
||||
|
||||
uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
|
||||
This parameter can be a value of @ref USART_Stop_Bits */
|
||||
|
||||
uint16_t USART_Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref USART_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_Mode */
|
||||
|
||||
uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
|
||||
or disabled.
|
||||
This parameter can be a value of @ref USART_Hardware_Flow_Control */
|
||||
} USART_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief USART Clock Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_Clock */
|
||||
|
||||
uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock.
|
||||
This parameter can be a value of @ref USART_Clock_Polarity */
|
||||
|
||||
uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
|
||||
This parameter can be a value of @ref USART_Clock_Phase */
|
||||
|
||||
uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
|
||||
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||
This parameter can be a value of @ref USART_Last_Bit */
|
||||
} USART_ClockInitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
|
||||
((PERIPH) == USART2) || \
|
||||
((PERIPH) == USART3) || \
|
||||
((PERIPH) == UART4) || \
|
||||
((PERIPH) == UART5))
|
||||
|
||||
#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
|
||||
((PERIPH) == USART2) || \
|
||||
((PERIPH) == USART3))
|
||||
|
||||
#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \
|
||||
((PERIPH) == USART2) || \
|
||||
((PERIPH) == USART3) || \
|
||||
((PERIPH) == UART4))
|
||||
/** @defgroup USART_Word_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_WordLength_8b ((uint16_t)0x0000)
|
||||
#define USART_WordLength_9b ((uint16_t)0x1000)
|
||||
|
||||
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
|
||||
((LENGTH) == USART_WordLength_9b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Stop_Bits
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_StopBits_1 ((uint16_t)0x0000)
|
||||
#define USART_StopBits_0_5 ((uint16_t)0x1000)
|
||||
#define USART_StopBits_2 ((uint16_t)0x2000)
|
||||
#define USART_StopBits_1_5 ((uint16_t)0x3000)
|
||||
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
|
||||
((STOPBITS) == USART_StopBits_0_5) || \
|
||||
((STOPBITS) == USART_StopBits_2) || \
|
||||
((STOPBITS) == USART_StopBits_1_5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Parity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Parity_No ((uint16_t)0x0000)
|
||||
#define USART_Parity_Even ((uint16_t)0x0400)
|
||||
#define USART_Parity_Odd ((uint16_t)0x0600)
|
||||
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
|
||||
((PARITY) == USART_Parity_Even) || \
|
||||
((PARITY) == USART_Parity_Odd))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Mode_Rx ((uint16_t)0x0004)
|
||||
#define USART_Mode_Tx ((uint16_t)0x0008)
|
||||
#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Hardware_Flow_Control
|
||||
* @{
|
||||
*/
|
||||
#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
|
||||
#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
|
||||
#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
|
||||
#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
|
||||
#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
|
||||
(((CONTROL) == USART_HardwareFlowControl_None) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_RTS) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_CTS) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock
|
||||
* @{
|
||||
*/
|
||||
#define USART_Clock_Disable ((uint16_t)0x0000)
|
||||
#define USART_Clock_Enable ((uint16_t)0x0800)
|
||||
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
|
||||
((CLOCK) == USART_Clock_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_CPOL_Low ((uint16_t)0x0000)
|
||||
#define USART_CPOL_High ((uint16_t)0x0400)
|
||||
#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Phase
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_CPHA_1Edge ((uint16_t)0x0000)
|
||||
#define USART_CPHA_2Edge ((uint16_t)0x0200)
|
||||
#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Last_Bit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_LastBit_Disable ((uint16_t)0x0000)
|
||||
#define USART_LastBit_Enable ((uint16_t)0x0100)
|
||||
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
|
||||
((LASTBIT) == USART_LastBit_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Interrupt_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_IT_PE ((uint16_t)0x0028)
|
||||
#define USART_IT_TXE ((uint16_t)0x0727)
|
||||
#define USART_IT_TC ((uint16_t)0x0626)
|
||||
#define USART_IT_RXNE ((uint16_t)0x0525)
|
||||
#define USART_IT_IDLE ((uint16_t)0x0424)
|
||||
#define USART_IT_LBD ((uint16_t)0x0846)
|
||||
#define USART_IT_CTS ((uint16_t)0x096A)
|
||||
#define USART_IT_ERR ((uint16_t)0x0060)
|
||||
#define USART_IT_ORE ((uint16_t)0x0360)
|
||||
#define USART_IT_NE ((uint16_t)0x0260)
|
||||
#define USART_IT_FE ((uint16_t)0x0160)
|
||||
#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
|
||||
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
|
||||
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
|
||||
#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
|
||||
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
|
||||
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
|
||||
((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
|
||||
#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||
((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_DMA_Requests
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_DMAReq_Tx ((uint16_t)0x0080)
|
||||
#define USART_DMAReq_Rx ((uint16_t)0x0040)
|
||||
#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_WakeUp_methods
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
|
||||
#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
|
||||
#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
|
||||
((WAKEUP) == USART_WakeUp_AddressMark))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_LIN_Break_Detection_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
|
||||
#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
|
||||
#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
|
||||
(((LENGTH) == USART_LINBreakDetectLength_10b) || \
|
||||
((LENGTH) == USART_LINBreakDetectLength_11b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_IrDA_Low_Power
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
|
||||
#define USART_IrDAMode_Normal ((uint16_t)0x0000)
|
||||
#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
|
||||
((MODE) == USART_IrDAMode_Normal))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_FLAG_CTS ((uint16_t)0x0200)
|
||||
#define USART_FLAG_LBD ((uint16_t)0x0100)
|
||||
#define USART_FLAG_TXE ((uint16_t)0x0080)
|
||||
#define USART_FLAG_TC ((uint16_t)0x0040)
|
||||
#define USART_FLAG_RXNE ((uint16_t)0x0020)
|
||||
#define USART_FLAG_IDLE ((uint16_t)0x0010)
|
||||
#define USART_FLAG_ORE ((uint16_t)0x0008)
|
||||
#define USART_FLAG_NE ((uint16_t)0x0004)
|
||||
#define USART_FLAG_FE ((uint16_t)0x0002)
|
||||
#define USART_FLAG_PE ((uint16_t)0x0001)
|
||||
#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
|
||||
((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
|
||||
((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
|
||||
((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
|
||||
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
|
||||
|
||||
#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
|
||||
#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\
|
||||
((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
|
||||
|| ((USART_FLAG) != USART_FLAG_CTS))
|
||||
#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
|
||||
#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
|
||||
#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void USART_DeInit(USART_TypeDef* USARTx);
|
||||
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
|
||||
void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
|
||||
void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
|
||||
void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
|
||||
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
|
||||
void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
|
||||
void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
|
||||
void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
|
||||
void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
|
||||
void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
|
||||
uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
|
||||
void USART_SendBreak(USART_TypeDef* USARTx);
|
||||
void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
|
||||
void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
|
||||
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
|
||||
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
|
||||
void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
|
||||
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
|
||||
void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_USART_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,224 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_wwdg.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file provides all the WWDG firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_wwdg.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG
|
||||
* @brief WWDG driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ----------- WWDG registers bit address in the alias region ----------- */
|
||||
#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
|
||||
|
||||
/* Alias word address of EWI bit */
|
||||
#define CFR_OFFSET (WWDG_OFFSET + 0x04)
|
||||
#define EWI_BitNumber 0x09
|
||||
#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
|
||||
|
||||
/* --------------------- WWDG registers bit mask ------------------------ */
|
||||
|
||||
/* CR register bit mask */
|
||||
#define CR_WDGA_Set ((uint32_t)0x00000080)
|
||||
|
||||
/* CFR register bit mask */
|
||||
#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
|
||||
#define CFR_W_Mask ((uint32_t)0xFFFFFF80)
|
||||
#define BIT_Mask ((uint8_t)0x7F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the WWDG peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_DeInit(void)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the WWDG Prescaler.
|
||||
* @param WWDG_Prescaler: specifies the WWDG Prescaler.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
|
||||
* @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
|
||||
* @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
|
||||
* @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
|
||||
/* Clear WDGTB[1:0] bits */
|
||||
tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
|
||||
/* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
|
||||
tmpreg |= WWDG_Prescaler;
|
||||
/* Store the new value */
|
||||
WWDG->CFR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the WWDG window value.
|
||||
* @param WindowValue: specifies the window value to be compared to the downcounter.
|
||||
* This parameter value must be lower than 0x80.
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_SetWindowValue(uint8_t WindowValue)
|
||||
{
|
||||
__IO uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
|
||||
/* Clear W[6:0] bits */
|
||||
|
||||
tmpreg = WWDG->CFR & CFR_W_Mask;
|
||||
|
||||
/* Set W[6:0] bits according to WindowValue value */
|
||||
tmpreg |= WindowValue & (uint32_t) BIT_Mask;
|
||||
|
||||
/* Store the new value */
|
||||
WWDG->CFR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the WWDG Early Wakeup interrupt(EWI).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_EnableIT(void)
|
||||
{
|
||||
*(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the WWDG counter value.
|
||||
* @param Counter: specifies the watchdog counter value.
|
||||
* This parameter must be a number between 0x40 and 0x7F.
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_SetCounter(uint8_t Counter)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_COUNTER(Counter));
|
||||
/* Write to T[6:0] bits to configure the counter value, no need to do
|
||||
a read-modify-write; writing a 0 to WDGA bit does nothing */
|
||||
WWDG->CR = Counter & BIT_Mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables WWDG and load the counter value.
|
||||
* @param Counter: specifies the watchdog counter value.
|
||||
* This parameter must be a number between 0x40 and 0x7F.
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_Enable(uint8_t Counter)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_COUNTER(Counter));
|
||||
WWDG->CR = CR_WDGA_Set | Counter;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the Early Wakeup interrupt flag is set or not.
|
||||
* @param None
|
||||
* @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
|
||||
*/
|
||||
FlagStatus WWDG_GetFlagStatus(void)
|
||||
{
|
||||
return (FlagStatus)(WWDG->SR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears Early Wakeup interrupt flag.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_ClearFlag(void)
|
||||
{
|
||||
WWDG->SR = (uint32_t)RESET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,115 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f10x_wwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief This file contains all the functions prototypes for the WWDG firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_WWDG_H
|
||||
#define __STM32F10x_WWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
|
||||
#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
|
||||
#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
|
||||
#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
|
||||
#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
|
||||
((PRESCALER) == WWDG_Prescaler_2) || \
|
||||
((PRESCALER) == WWDG_Prescaler_4) || \
|
||||
((PRESCALER) == WWDG_Prescaler_8))
|
||||
#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
|
||||
#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void WWDG_DeInit(void);
|
||||
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
|
||||
void WWDG_SetWindowValue(uint8_t WindowValue);
|
||||
void WWDG_EnableIT(void);
|
||||
void WWDG_SetCounter(uint8_t Counter);
|
||||
void WWDG_Enable(uint8_t Counter);
|
||||
FlagStatus WWDG_GetFlagStatus(void);
|
||||
void WWDG_ClearFlag(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_WWDG_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because one or more lines are too long
+3609
File diff suppressed because one or more lines are too long
+1076
File diff suppressed because it is too large
Load Diff
+761
@@ -0,0 +1,761 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>Target 1</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>5060183::V5.06 update 2 (build 183)::ARMCC</pCCUsed>
|
||||
<uAC6>0</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>STM32F103C8</Device>
|
||||
<Vendor>STMicroelectronics</Vendor>
|
||||
<PackID>Keil.STM32F1xx_DFP.1.1.0</PackID>
|
||||
<PackURL>http://www.keil.com/pack/</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0x5000) IROM(0x08000000,0x10000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103C8$Flash\STM32F10x_128.FLM))</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:STM32F103C8$Device\Include\stm32f10x.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:STM32F103C8$SVD\STM32F103xx.svd</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\Objects\</OutputDirectory>
|
||||
<OutputName>Project</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments> -REMAP</SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM3</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments></TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>0</Capability>
|
||||
<DriverSelection>-1</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3></Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M3"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>0</RvdsVP>
|
||||
<hadIRAM2>0</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>1</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x5000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x10000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x10000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x5000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>1</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>1</v6Lang>
|
||||
<v6LangP>1</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls>--no-multibyte-chars</MiscControls>
|
||||
<Define>STM32F10X_MD,USE_STDPERIPH_DRIVER</Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath>.\Start;.\Library;.\User;.\System;.\Hardware</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<uClangAs>0</uClangAs>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>1</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x08000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile></ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>Start</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>startup_stm32f10x_md.s</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>.\Start\startup_stm32f10x_md.s</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>core_cm3.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Start\core_cm3.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>core_cm3.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Start\core_cm3.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Start\stm32f10x.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>system_stm32f10x.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Start\system_stm32f10x.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>system_stm32f10x.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Start\system_stm32f10x.h</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Library</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>misc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Library\misc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>misc.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Library\misc.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_adc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Library\stm32f10x_adc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_adc.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Library\stm32f10x_adc.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_bkp.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Library\stm32f10x_bkp.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_bkp.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Library\stm32f10x_bkp.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_can.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Library\stm32f10x_can.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_can.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Library\stm32f10x_can.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_cec.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Library\stm32f10x_cec.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_cec.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Library\stm32f10x_cec.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_crc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Library\stm32f10x_crc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_crc.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Library\stm32f10x_crc.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_dac.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Library\stm32f10x_dac.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_dac.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Library\stm32f10x_dac.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_dbgmcu.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Library\stm32f10x_dbgmcu.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_dbgmcu.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Library\stm32f10x_dbgmcu.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_dma.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Library\stm32f10x_dma.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_dma.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Library\stm32f10x_dma.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_exti.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Library\stm32f10x_exti.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_exti.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Library\stm32f10x_exti.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_flash.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Library\stm32f10x_flash.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_flash.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Library\stm32f10x_flash.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_fsmc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Library\stm32f10x_fsmc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_fsmc.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Library\stm32f10x_fsmc.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_gpio.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Library\stm32f10x_gpio.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_gpio.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Library\stm32f10x_gpio.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_i2c.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Library\stm32f10x_i2c.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_i2c.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Library\stm32f10x_i2c.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_iwdg.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Library\stm32f10x_iwdg.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_iwdg.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Library\stm32f10x_iwdg.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_pwr.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Library\stm32f10x_pwr.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_pwr.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Library\stm32f10x_pwr.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_rcc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Library\stm32f10x_rcc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_rcc.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Library\stm32f10x_rcc.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_rtc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Library\stm32f10x_rtc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_rtc.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Library\stm32f10x_rtc.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_sdio.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Library\stm32f10x_sdio.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_sdio.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Library\stm32f10x_sdio.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_spi.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Library\stm32f10x_spi.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_spi.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Library\stm32f10x_spi.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_tim.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Library\stm32f10x_tim.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_tim.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Library\stm32f10x_tim.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_usart.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Library\stm32f10x_usart.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_usart.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Library\stm32f10x_usart.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_wwdg.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Library\stm32f10x_wwdg.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_wwdg.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Library\stm32f10x_wwdg.h</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>System</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>Delay.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\System\Delay.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>Debug.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\System\Debug.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Hardware</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>OLED.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Hardware\OLED.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>Serial.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Hardware\Serial.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>esp8266.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Hardware\esp8266.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>Buzzer_LED.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Hardware\Buzzer_LED.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>K210_USART.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Hardware\K210_USART.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>Attendance.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Hardware\Attendance.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>aes.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Hardware\aes.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>base64.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Hardware\base64.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>Crypto.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Hardware\Crypto.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>DS1302.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Hardware\DS1302.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>LightSensor.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\Hardware\LightSensor.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>User</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>main.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\User\main.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_conf.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\User\stm32f10x_conf.h</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_it.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\User\stm32f10x_it.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_it.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\User\stm32f10x_it.h</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis/>
|
||||
<components/>
|
||||
<files/>
|
||||
</RTE>
|
||||
|
||||
</Project>
|
||||
@@ -0,0 +1,59 @@
|
||||
# Build directories
|
||||
build/
|
||||
build-*/
|
||||
cmake-build-*/
|
||||
out/
|
||||
dist/
|
||||
|
||||
# CMake generated files
|
||||
CMakeCache.txt
|
||||
CMakeFiles/
|
||||
cmake_install.cmake
|
||||
install_manifest.txt
|
||||
compile_commands.json
|
||||
CTestTestfile.cmake
|
||||
DartConfiguration.tcl
|
||||
|
||||
# Qt Creator local settings
|
||||
.qtcreator/
|
||||
*.user
|
||||
*.user.*
|
||||
|
||||
# Qt generated artifacts
|
||||
*_autogen/
|
||||
*.qmlc
|
||||
*.jsc
|
||||
qrc_*.cpp
|
||||
moc_*.cpp
|
||||
moc_*.h
|
||||
ui_*.h
|
||||
|
||||
# Compiled binaries and libraries
|
||||
*.exe
|
||||
*.dll
|
||||
*.so
|
||||
*.dylib
|
||||
*.a
|
||||
*.lib
|
||||
*.o
|
||||
*.obj
|
||||
*.pdb
|
||||
*.ilk
|
||||
|
||||
# Android build outputs
|
||||
android-build/
|
||||
*.apk
|
||||
*.aab
|
||||
|
||||
# Logs and temporary files
|
||||
*.log
|
||||
*.tmp
|
||||
*.temp
|
||||
*.bak
|
||||
*.swp
|
||||
*~
|
||||
|
||||
# OS files
|
||||
.DS_Store
|
||||
Thumbs.db
|
||||
desktop.ini
|
||||
@@ -0,0 +1,145 @@
|
||||
cmake_minimum_required(VERSION 3.16)
|
||||
|
||||
project(rewrite_qt VERSION 1.0.0 LANGUAGES CXX)
|
||||
|
||||
set(REWRITE_QT_DISPLAY_NAME "人脸识别考勤系统")
|
||||
set(QT_QML_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/qml")
|
||||
set(REWRITE_QT_OUTPUT_DIR "${CMAKE_CURRENT_SOURCE_DIR}/dist")
|
||||
set(CMAKE_RUNTIME_OUTPUT_DIRECTORY "${REWRITE_QT_OUTPUT_DIR}")
|
||||
set(CMAKE_LIBRARY_OUTPUT_DIRECTORY "${REWRITE_QT_OUTPUT_DIR}")
|
||||
set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY "${REWRITE_QT_OUTPUT_DIR}")
|
||||
set(CMAKE_CXX_STANDARD 17)
|
||||
set(CMAKE_CXX_STANDARD_REQUIRED ON)
|
||||
set(CMAKE_AUTOMOC ON)
|
||||
set(CMAKE_AUTOMOC_COMPILER_PREDEFINES OFF)
|
||||
set(CMAKE_AUTORCC ON)
|
||||
|
||||
file(TO_CMAKE_PATH "$ENV{LOCALAPPDATA}" REWRITE_QT_LOCALAPPDATA)
|
||||
if(REWRITE_QT_LOCALAPPDATA)
|
||||
set(REWRITE_QT_AUTOGEN_DIR "${REWRITE_QT_LOCALAPPDATA}/rewrite_qt_autogen")
|
||||
else()
|
||||
set(REWRITE_QT_AUTOGEN_DIR "${CMAKE_BINARY_DIR}/autogen_ascii")
|
||||
endif()
|
||||
file(MAKE_DIRECTORY "${REWRITE_QT_AUTOGEN_DIR}")
|
||||
|
||||
find_package(Qt6 6.2 REQUIRED COMPONENTS Core Gui Qml Quick QuickControls2 Network)
|
||||
|
||||
get_target_property(REWRITE_QT_QMAKE_EXECUTABLE Qt6::qmake IMPORTED_LOCATION)
|
||||
if(REWRITE_QT_QMAKE_EXECUTABLE)
|
||||
execute_process(
|
||||
COMMAND "${REWRITE_QT_QMAKE_EXECUTABLE}" -query QT_INSTALL_QML
|
||||
OUTPUT_VARIABLE REWRITE_QT_INSTALL_QML
|
||||
OUTPUT_STRIP_TRAILING_WHITESPACE
|
||||
)
|
||||
endif()
|
||||
|
||||
qt_standard_project_setup()
|
||||
|
||||
set(REWRITE_QT_APP_ICON "${CMAKE_CURRENT_SOURCE_DIR}/assets/favicon.ico")
|
||||
set(REWRITE_QT_ICON_RESOURCES
|
||||
assets/favicon.ico
|
||||
assets/favicon-256x256.png
|
||||
assets/favicon-192x192.png
|
||||
assets/favicon-128x128.png
|
||||
assets/favicon-64x64.png
|
||||
assets/favicon-48x48.png
|
||||
assets/favicon-32x32.png
|
||||
assets/favicon-16x16.png
|
||||
)
|
||||
|
||||
qt_add_executable(apprewrite_qt
|
||||
main.cpp
|
||||
src/AppController.cpp
|
||||
src/ApiClient.cpp
|
||||
src/CryptoUtils.cpp
|
||||
src/RecordListModel.cpp
|
||||
src/StatisticsListModel.cpp
|
||||
src/TimeSlotListModel.cpp
|
||||
src/MappingListModel.cpp
|
||||
src/FaceListModel.cpp
|
||||
)
|
||||
|
||||
if(REWRITE_QT_INSTALL_QML)
|
||||
target_compile_definitions(apprewrite_qt PRIVATE
|
||||
REWRITE_QT_INSTALL_QML="${REWRITE_QT_INSTALL_QML}"
|
||||
)
|
||||
endif()
|
||||
|
||||
if(WIN32 AND EXISTS "${REWRITE_QT_APP_ICON}")
|
||||
set(REWRITE_QT_WIN32_ICON_RC "${CMAKE_CURRENT_BINARY_DIR}/app_icon.rc")
|
||||
configure_file(cmake/app_icon.rc.in "${REWRITE_QT_WIN32_ICON_RC}" @ONLY)
|
||||
target_sources(apprewrite_qt PRIVATE "${REWRITE_QT_WIN32_ICON_RC}")
|
||||
endif()
|
||||
|
||||
if(ANDROID)
|
||||
set_target_properties(apprewrite_qt PROPERTIES
|
||||
QT_ANDROID_PACKAGE_SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/android"
|
||||
QT_ANDROID_APP_NAME "${REWRITE_QT_DISPLAY_NAME}"
|
||||
QT_ANDROID_APP_ICON "@mipmap/ic_launcher"
|
||||
)
|
||||
endif()
|
||||
|
||||
target_include_directories(apprewrite_qt PRIVATE
|
||||
${CMAKE_CURRENT_SOURCE_DIR}/src
|
||||
)
|
||||
|
||||
set(REWRITE_QT_RESOURCE_FILES
|
||||
qml/Main.qml
|
||||
)
|
||||
|
||||
foreach(REWRITE_QT_ICON_RESOURCE IN LISTS REWRITE_QT_ICON_RESOURCES)
|
||||
if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${REWRITE_QT_ICON_RESOURCE}")
|
||||
list(APPEND REWRITE_QT_RESOURCE_FILES "${REWRITE_QT_ICON_RESOURCE}")
|
||||
endif()
|
||||
endforeach()
|
||||
|
||||
qt_add_resources(apprewrite_qt "qml_resources"
|
||||
PREFIX "/"
|
||||
FILES
|
||||
${REWRITE_QT_RESOURCE_FILES}
|
||||
)
|
||||
|
||||
target_link_libraries(apprewrite_qt
|
||||
PRIVATE
|
||||
Qt6::Core
|
||||
Qt6::Gui
|
||||
Qt6::Qml
|
||||
Qt6::Quick
|
||||
Qt6::QuickControls2
|
||||
Qt6::Network
|
||||
)
|
||||
|
||||
set_target_properties(apprewrite_qt PROPERTIES
|
||||
AUTOGEN_BUILD_DIR "${REWRITE_QT_AUTOGEN_DIR}"
|
||||
QT_QML_MODULE_NO_IMPORT_SCAN TRUE
|
||||
MACOSX_BUNDLE_BUNDLE_VERSION ${PROJECT_VERSION}
|
||||
MACOSX_BUNDLE_SHORT_VERSION_STRING ${PROJECT_VERSION_MAJOR}.${PROJECT_VERSION_MINOR}
|
||||
MACOSX_BUNDLE TRUE
|
||||
WIN32_EXECUTABLE TRUE
|
||||
)
|
||||
|
||||
include(GNUInstallDirs)
|
||||
|
||||
if(UNIX AND NOT APPLE AND NOT ANDROID)
|
||||
set(REWRITE_QT_DESKTOP_FILE "${CMAKE_CURRENT_BINARY_DIR}/rewrite_qt.desktop")
|
||||
configure_file(cmake/rewrite_qt.desktop.in "${REWRITE_QT_DESKTOP_FILE}" @ONLY)
|
||||
install(FILES "${REWRITE_QT_DESKTOP_FILE}"
|
||||
DESTINATION "${CMAKE_INSTALL_DATAROOTDIR}/applications"
|
||||
)
|
||||
|
||||
foreach(REWRITE_QT_ICON_SIZE IN ITEMS 16 32 48 64 128 192 256)
|
||||
set(REWRITE_QT_LINUX_ICON "${CMAKE_CURRENT_SOURCE_DIR}/assets/favicon-${REWRITE_QT_ICON_SIZE}x${REWRITE_QT_ICON_SIZE}.png")
|
||||
if(EXISTS "${REWRITE_QT_LINUX_ICON}")
|
||||
install(FILES "${REWRITE_QT_LINUX_ICON}"
|
||||
DESTINATION "${CMAKE_INSTALL_DATAROOTDIR}/icons/hicolor/${REWRITE_QT_ICON_SIZE}x${REWRITE_QT_ICON_SIZE}/apps"
|
||||
RENAME rewrite_qt.png
|
||||
)
|
||||
endif()
|
||||
endforeach()
|
||||
endif()
|
||||
|
||||
install(TARGETS apprewrite_qt
|
||||
BUNDLE DESTINATION .
|
||||
RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}
|
||||
LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}
|
||||
)
|
||||
+21
@@ -0,0 +1,21 @@
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2026 Jitianye
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
+517
@@ -0,0 +1,517 @@
|
||||
# 人脸识别考勤系统
|
||||
|
||||
基于 Qt 6 Quick/QML 开发的跨平台人脸识别考勤管理客户端，用于连接考勤服务端，完成签到记录查看、筛选导出、统计分析、签到时段配置、学生与班级名称映射、人脸照片与学号绑定等管理工作。
|
||||
|
||||
本项目是纪田野的个人毕业设计作品，主要用于人脸识别考勤场景的功能展示、系统联调和学习研究。
|
||||
|
||||
## 项目特点
|
||||
|
||||
- 跨平台客户端：支持 Windows 桌面端和 Android 端构建。
|
||||
- 单窗口管理：考勤记录、统计分析、配置中心、人脸管理和系统说明集中在一个界面中。
|
||||
- 响应式界面：针对手机窄屏做了独立布局适配，避免控件重叠和文字遮挡。
|
||||
- 数据导出：支持将考勤记录和统计报表导出为 CSV 文件。
|
||||
- 本地配置缓存：服务端地址、签到时段、映射配置会保存到本地。
|
||||
- 自动重连：服务端不可达时自动重连，并使用简短状态提示。
|
||||
- Android 字体优化：Android 端使用原生文字渲染，并降低粗体权重，减少中文粗体重影。
|
||||
- Android 路径兼容：Gradle 配置已允许中文路径构建，并启用 AndroidX。
|
||||
|
||||
## 技术栈
|
||||
|
||||
| 分类 | 内容 |
|
||||
| --- | --- |
|
||||
| 开发语言 | C++17、QML |
|
||||
| UI 框架 | Qt Quick / Qt Quick Controls 2 |
|
||||
| Qt 模块 | Core、Gui、Qml、Quick、QuickControls2、Network |
|
||||
| 构建系统 | CMake 3.16+ |
|
||||
| 桌面编译器 | MinGW / MSVC / Clang / GCC |
|
||||
| Android 构建 | Qt for Android、Android SDK、Android NDK、JDK |
|
||||
| 加密处理 | AES-128-CBC，代码位于 `src/CryptoUtils.cpp` |
|
||||
|
||||
## 目录结构
|
||||
|
||||
```text
|
||||
rewrite_qt/
|
||||
├── android/ # Android 打包补充资源和 Gradle 配置
|
||||
│ ├── gradle.properties
|
||||
│ └── res/mipmap-*/ # Android 启动图标
|
||||
├── assets/ # 桌面端图标资源
|
||||
├── cmake/ # 平台相关模板文件
|
||||
├── qml/
|
||||
│ └── Main.qml # 主界面
|
||||
├── src/
|
||||
│ ├── ApiClient.* # 服务端 API 客户端
|
||||
│ ├── AppController.* # QML 与业务逻辑中枢
|
||||
│ ├── AttendanceTypes.h # 考勤数据结构
|
||||
│ ├── CryptoUtils.* # AES 解密工具
|
||||
│ ├── *ListModel.* # 暴露给 QML 的列表模型
|
||||
│ └── crypto/tiny_aes.hpp # AES 底层实现
|
||||
├── CMakeLists.txt
|
||||
├── LICENSE
|
||||
├── README.md
|
||||
└── main.cpp
|
||||
```
|
||||
|
||||
## 功能说明
|
||||
|
||||
### 考勤记录
|
||||
|
||||
考勤记录页用于查看和管理服务端同步下来的签到记录。
|
||||
|
||||
- 查看总记录数、今日签到数、当前筛选结果数。
|
||||
- 按班级、学号、姓名关键字筛选记录。
|
||||
- 按全部时间、今天、最近 7 天、最近 30 天、指定日期筛选。
|
||||
- 刷新最新记录。
|
||||
- 导出当前筛选结果为 CSV。
|
||||
- 清空服务端全部考勤记录。
|
||||
|
||||
导出字段：
|
||||
|
||||
```text
|
||||
签到时间,班级编号,班级名称,学号,姓名,置信度,状态
|
||||
```
|
||||
|
||||
### 统计分析
|
||||
|
||||
统计分析页基于当前加载的考勤记录在本地计算统计结果。
|
||||
|
||||
- 支持今天、最近 7 天、最近 30 天、本月等快捷范围。
|
||||
- 支持手动指定开始日期和结束日期。
|
||||
- 展示统计学生数、统计记录数、统计范围。
|
||||
- 按学生汇总总签到次数、今日签到次数、最后签到时间和平均置信度。
|
||||
- 导出统计报表为 CSV。
|
||||
|
||||
导出字段：
|
||||
|
||||
```text
|
||||
学号,姓名,总签到次数,今日签到,最后签到时间,平均置信度
|
||||
```
|
||||
|
||||
### 配置中心
|
||||
|
||||
配置中心用于维护客户端与服务端交互所需的配置。
|
||||
|
||||
- 设置服务端地址。
|
||||
- 测试服务端连接状态。
|
||||
- 管理签到时段。
|
||||
- 从服务端同步签到时段。
|
||||
- 管理学号到姓名的映射。
|
||||
- 管理班级编号到班级名称的映射。
|
||||
- 保存配置并同步到服务端。
|
||||
|
||||
默认签到时段：
|
||||
|
||||
| 名称 | 开始时间 | 结束时间 | 默认状态 |
|
||||
| --- | --- | --- | --- |
|
||||
| 上午签到 | 08:00 | 09:30 | 启用 |
|
||||
| 中午签退 | 12:00 | 13:00 | 启用 |
|
||||
| 下午签到 | 14:00 | 15:00 | 启用 |
|
||||
| 晚上签退 | 17:00 | 18:30 | 启用 |
|
||||
|
||||
### 人脸管理
|
||||
|
||||
人脸管理页用于维护 K210 上传的人脸照片记录与真实学号之间的映射关系。
|
||||
|
||||
- 同步人脸照片 ID。
|
||||
- 同步服务端学生 ID。
|
||||
- 展示人脸照片或无照片状态。
|
||||
- 为人脸 ID 绑定真实学号。
|
||||
- 保存人脸 ID 与学号映射。
|
||||
- 删除指定人脸信息。
|
||||
- 可选择同时删除该学生相关考勤记录。
|
||||
|
||||
照片访问地址格式：
|
||||
|
||||
```text
|
||||
{serverUrl}/api/face_photo/{id}?ts={timestamp}
|
||||
```
|
||||
|
||||
其中 `ts` 用于避免缓存导致照片不刷新。
|
||||
|
||||
## 服务端配置
|
||||
|
||||
默认服务端地址：
|
||||
|
||||
```text
|
||||
http://127.0.0.1:8082
|
||||
```
|
||||
|
||||
应用启动后会从本地配置读取已保存的服务端地址。用户可在“配置中心”中修改并保存。
|
||||
|
||||
本地保存键名：
|
||||
|
||||
```text
|
||||
server/url
|
||||
```
|
||||
|
||||
## 服务端 API
|
||||
|
||||
客户端会基于服务端地址拼接 `/api` 前缀访问接口。
|
||||
|
||||
| 方法 | 路径 | 用途 |
|
||||
| --- | --- | --- |
|
||||
| `GET` | `/api/records?limit={limit}&offset={offset}` | 获取考勤记录 |
|
||||
| `GET` | `/api/statistics` | 获取总数、今日数和服务端时间 |
|
||||
| `POST` | `/api/clear` | 清空全部记录 |
|
||||
| `DELETE` | `/api/record?timestamp={timestamp}&student_id={studentId}` | 删除单条记录 |
|
||||
| `GET` | `/api/timeslots` | 获取签到时段 |
|
||||
| `POST` | `/api/timeslots` | 保存签到时段 |
|
||||
| `GET` | `/api/mapping_config` | 获取学生和班级映射 |
|
||||
| `POST` | `/api/mapping_config` | 保存学生和班级映射 |
|
||||
| `GET` | `/api/face_id_mapping` | 获取人脸 ID 到学号映射 |
|
||||
| `POST` | `/api/face_id_mapping` | 保存人脸 ID 到学号映射 |
|
||||
| `GET` | `/api/face_photos` | 获取照片 ID 列表 |
|
||||
| `GET` | `/api/all_student_ids` | 获取所有学生 ID |
|
||||
| `GET` | `/api/face_photo/{id}` | 获取人脸照片 |
|
||||
| `DELETE` | `/api/face/{studentId}` | 删除人脸信息 |
|
||||
| `DELETE` | `/api/face/{studentId}?delete_records=true` | 删除人脸信息并删除相关考勤记录 |
|
||||
| `GET` | `/api/health` | 健康检查 |
|
||||
|
||||
### 考勤记录格式
|
||||
|
||||
`/api/records` 解密后应返回 JSON 数组。单条记录示例：
|
||||
|
||||
```json
|
||||
{
|
||||
"timestamp": "2026-04-24 08:10:23",
|
||||
"student_id": "20240001",
|
||||
"name": "张三",
|
||||
"confidence": 0.9821,
|
||||
"status": "success",
|
||||
"class_id": "1"
|
||||
}
|
||||
```
|
||||
|
||||
### 统计数据格式
|
||||
|
||||
```json
|
||||
{
|
||||
"total": 120,
|
||||
"today": 8,
|
||||
"server_time": "2026-04-24 10:30:00"
|
||||
}
|
||||
```
|
||||
|
||||
### 签到时段格式
|
||||
|
||||
```json
|
||||
{
|
||||
"time_slots": [
|
||||
{
|
||||
"name": "上午签到",
|
||||
"start_time": "08:00",
|
||||
"end_time": "09:30",
|
||||
"enabled": true
|
||||
}
|
||||
]
|
||||
}
|
||||
```
|
||||
|
||||
### 映射配置格式
|
||||
|
||||
```json
|
||||
{
|
||||
"student_name_map": {
|
||||
"20240001": "张三"
|
||||
},
|
||||
"class_name_map": {
|
||||
"1": "软件工程一班"
|
||||
}
|
||||
}
|
||||
```
|
||||
|
||||
### 人脸映射格式
|
||||
|
||||
```json
|
||||
{
|
||||
"mappings": {
|
||||
"face_001": "20240001"
|
||||
}
|
||||
}
|
||||
```
|
||||
|
||||
## 加密响应
|
||||
|
||||
客户端对 `/api/records` 和 `/api/statistics` 请求添加请求头：
|
||||
|
||||
```text
|
||||
X-Encrypted-Response: true
|
||||
```
|
||||
|
||||
客户端期望服务端返回 Base64 编码的 AES-128-CBC 密文。
|
||||
|
||||
解密参数位于 `src/CryptoUtils.cpp`：
|
||||
|
||||
| 参数 | 值 |
|
||||
| --- | --- |
|
||||
| 算法 | AES-128-CBC |
|
||||
| Padding | PKCS#7 |
|
||||
| Key | `2b 7e 15 16 28 ae d2 a6 ab f7 15 88 09 cf 4f 3c` |
|
||||
| IV | `00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f` |
|
||||
|
||||
## 本地配置文件
|
||||
|
||||
应用使用 `QSettings` 和 `QStandardPaths::AppDataLocation` 保存本地状态。
|
||||
|
||||
| 配置 | 保存位置 |
|
||||
| --- | --- |
|
||||
| 服务端地址 | `QSettings`，键名 `server/url` |
|
||||
| 学生和班级映射 | `mapping_config.json` |
|
||||
| 签到时段配置 | `timeslot_config.json` |
|
||||
|
||||
应用信息：
|
||||
|
||||
```text
|
||||
ApplicationName: 人脸识别考勤系统
|
||||
ApplicationVersion: 3.0.0
|
||||
OrganizationName: STM32 Face Recognition
|
||||
```
|
||||
|
||||
## 构建环境
|
||||
|
||||
### 基础要求
|
||||
|
||||
- Qt 6.2 或更高版本
|
||||
- CMake 3.16 或更高版本
|
||||
- 支持 C++17 的编译器
|
||||
|
||||
Windows 桌面端推荐使用 Qt 6.x MinGW 64-bit Kit。
|
||||
|
||||
Android 端需要额外配置：
|
||||
|
||||
- Qt for Android
|
||||
- Android SDK
|
||||
- Android NDK
|
||||
- JDK
|
||||
- Android 平台版本，例如 `android-35`
|
||||
|
||||
## 使用 Qt Creator 构建
|
||||
|
||||
1. 打开 Qt Creator。
|
||||
2. 选择项目根目录下的 `CMakeLists.txt`。
|
||||
3. 选择对应 Kit，例如 Desktop Qt 6.x 或 Qt for Android。
|
||||
4. 等待 CMake 配置完成。
|
||||
5. 构建目标 `apprewrite_qt`。
|
||||
6. 桌面端可直接运行；Android 端可部署到设备或模拟器。
|
||||
|
||||
## 命令行构建
|
||||
|
||||
Windows 示例：
|
||||
|
||||
```powershell
|
||||
cmake -S . -B build -DCMAKE_PREFIX_PATH=D:/Qt/6.10.0/mingw_64
|
||||
cmake --build build --target apprewrite_qt
|
||||
```
|
||||
|
||||
Linux 示例：
|
||||
|
||||
```bash
|
||||
cmake -S . -B build -DCMAKE_PREFIX_PATH=/path/to/Qt/6.x/gcc_64
|
||||
cmake --build build --target apprewrite_qt
|
||||
```
|
||||
|
||||
安装到系统路径：
|
||||
|
||||
```bash
|
||||
cmake --install build
|
||||
```
|
||||
|
||||
## Windows 独立运行
|
||||
|
||||
直接双击构建出来的 `apprewrite_qt.exe` 时，如果提示找不到 `Qt6Gui.dll`、`Qt6Core.dll` 等动态库，需要使用 `windeployqt` 收集运行时依赖。
|
||||
|
||||
示例：
|
||||
|
||||
```powershell
|
||||
D:\Qt\6.10.0\mingw_64\bin\windeployqt.exe "D:\path\to\build\Desktop_Qt_6_10_0_MinGW_64_bit-Debug\apprewrite_qt.exe"
|
||||
```
|
||||
|
||||
如果项目路径包含中文导致部署工具输出异常，建议复制 exe 到纯英文路径后部署：
|
||||
|
||||
```powershell
|
||||
mkdir C:\tmp\rewrite_qt_release
|
||||
copy "D:\path\to\apprewrite_qt.exe" C:\tmp\rewrite_qt_release\
|
||||
D:\Qt\6.10.0\mingw_64\bin\windeployqt.exe C:\tmp\rewrite_qt_release\apprewrite_qt.exe
|
||||
```
|
||||
|
||||
部署完成后，将整个发布目录一起复制到目标电脑运行。
|
||||
|
||||
## Android 构建说明
|
||||
|
||||
Android 相关配置位于 `CMakeLists.txt`：
|
||||
|
||||
```cmake
|
||||
QT_ANDROID_PACKAGE_SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/android"
|
||||
QT_ANDROID_APP_NAME "${REWRITE_QT_DISPLAY_NAME}"
|
||||
QT_ANDROID_APP_ICON "@mipmap/ic_launcher"
|
||||
```
|
||||
|
||||
Android 补充配置位于 `android/gradle.properties`：
|
||||
|
||||
```properties
|
||||
android.overridePathCheck=true
|
||||
android.useAndroidX=true
|
||||
```
|
||||
|
||||
说明：
|
||||
|
||||
- `android.overridePathCheck=true` 用于绕过 Windows 下 Android Gradle 对中文路径的检查。
|
||||
- `android.useAndroidX=true` 用于启用 AndroidX，避免依赖检查失败。
|
||||
- Android 桌面显示名由 `QT_ANDROID_APP_NAME` 设置为“人脸识别考勤系统”。
|
||||
- Android 启动图标位于 `android/res/mipmap-*`。
|
||||
|
||||
如果 Android 构建目录已经生成过旧的 Gradle 工程，修改配置后建议清理对应构建目录或重新运行 CMake 配置。
|
||||
|
||||
## 图标资源
|
||||
|
||||
桌面端图标位于 `assets/`：
|
||||
|
||||
```text
|
||||
assets/favicon.ico
|
||||
assets/favicon-16x16.png
|
||||
assets/favicon-32x32.png
|
||||
assets/favicon-48x48.png
|
||||
assets/favicon-64x64.png
|
||||
assets/favicon-128x128.png
|
||||
assets/favicon-192x192.png
|
||||
assets/favicon-256x256.png
|
||||
```
|
||||
|
||||
Android 启动图标位于：
|
||||
|
||||
```text
|
||||
android/res/mipmap-mdpi/ic_launcher.png
|
||||
android/res/mipmap-hdpi/ic_launcher.png
|
||||
android/res/mipmap-xhdpi/ic_launcher.png
|
||||
android/res/mipmap-xxhdpi/ic_launcher.png
|
||||
android/res/mipmap-xxxhdpi/ic_launcher.png
|
||||
```
|
||||
|
||||
图标尺寸：
|
||||
|
||||
| 目录 | 尺寸 |
|
||||
| --- | --- |
|
||||
| `mipmap-mdpi` | 48x48 |
|
||||
| `mipmap-hdpi` | 72x72 |
|
||||
| `mipmap-xhdpi` | 96x96 |
|
||||
| `mipmap-xxhdpi` | 144x144 |
|
||||
| `mipmap-xxxhdpi` | 192x192 |
|
||||
|
||||
## 界面与移动端适配
|
||||
|
||||
主界面位于 `qml/Main.qml`，采用 `ApplicationWindow`、`StackLayout`、`GridLayout`、`ColumnLayout` 等组件组织页面。
|
||||
|
||||
当前界面包含五个页面：
|
||||
|
||||
- 考勤记录
|
||||
- 统计分析
|
||||
- 配置中心
|
||||
- 人脸管理
|
||||
- 关于
|
||||
|
||||
移动端适配要点：
|
||||
|
||||
- `phoneLayout` 用于 560px 以下窄屏布局。
|
||||
- 顶部页签使用统一的 `MobileNavTabButton` 样式。
|
||||
- 考勤筛选区使用两列布局，按钮等宽排布。
|
||||
- 统计页前两张统计卡左右排布，统计范围独占一整行。
|
||||
- 表格在窄屏隐藏部分非关键列，避免横向溢出。
|
||||
- 空状态卡片会根据可用高度自动缩小。
|
||||
- Android 端使用 `sans-serif` 字体和 `Font.Medium` 加粗权重，减少粗体重影。
|
||||
|
||||
## 运行状态提示
|
||||
|
||||
客户端通过底部 Toast 展示状态信息。服务端不可达时，提示会被压缩为简短文案：
|
||||
|
||||
```text
|
||||
服务器未连接，稍后重试
|
||||
```
|
||||
|
||||
重连过程中显示：
|
||||
|
||||
```text
|
||||
正在重连服务器
|
||||
```
|
||||
|
||||
这样可以避免将底层网络错误、URL 和长异常文本直接展示给用户。
|
||||
|
||||
## 常见问题
|
||||
|
||||
### Android 构建提示项目路径包含中文
|
||||
|
||||
项目已经在 `android/gradle.properties` 中配置：
|
||||
|
||||
```properties
|
||||
android.overridePathCheck=true
|
||||
```
|
||||
|
||||
如果仍然失败，清理 Android 构建目录后重新构建。
|
||||
|
||||
### Android 构建提示 AndroidX 未启用
|
||||
|
||||
项目已经在 `android/gradle.properties` 中配置：
|
||||
|
||||
```properties
|
||||
android.useAndroidX=true
|
||||
```
|
||||
|
||||
如果旧构建目录仍然报错，删除生成的 `android-build-*` 目录后重新部署。
|
||||
|
||||
### Android 端粗体文字重影
|
||||
|
||||
项目在 Android 端启用了原生文字渲染：
|
||||
|
||||
```cpp
|
||||
QQuickWindow::setTextRenderType(QQuickWindow::NativeTextRendering);
|
||||
```
|
||||
|
||||
同时 QML 中将 Android 端粗体权重降为 `Font.Medium`，避免合成粗体产生重影。
|
||||
|
||||
### Windows 双击 exe 提示缺少 Qt DLL
|
||||
|
||||
使用 `windeployqt` 部署依赖后再运行。部署时建议使用和构建 Kit 一致的 Qt 目录。
|
||||
|
||||
### 修改图标后没有变化
|
||||
|
||||
重新运行 CMake 配置并重新构建。Windows 资源管理器可能缓存 exe 图标，可尝试换构建目录、改输出文件名或重启资源管理器。
|
||||
|
||||
### 启动后没有数据
|
||||
|
||||
检查服务端地址是否正确，并在配置中心点击“测试连接”。如果服务端不可达，底部会显示简短连接失败提示。
|
||||
|
||||
### 姓名或班级显示不正确
|
||||
|
||||
在配置中心维护学生姓名映射和班级名称映射，保存后记录列表和统计结果会重新计算。
|
||||
|
||||
### 人脸照片不显示
|
||||
|
||||
检查 `/api/face_photos` 是否返回照片 ID，并确认 `/api/face_photo/{id}` 可以访问。
|
||||
|
||||
## 仓库与作者
|
||||
|
||||
仓库地址：
|
||||
|
||||
```text
|
||||
ssh://git@git.yzfh.eu.cc:2084/yzfh/qt.git
|
||||
```
|
||||
|
||||
作者：
|
||||
|
||||
```text
|
||||
纪田野
|
||||
```
|
||||
|
||||
关于页中也展示了仓库地址和查看账号信息。若项目公开发布，请避免在仓库中提交真实密码。
|
||||
|
||||
## 维护建议
|
||||
|
||||
- 不要提交 `build/`、`build-codex/` 等构建目录。
|
||||
- 修改 QML 后建议运行 `qmlformat` 保持格式一致。
|
||||
- 服务端记录量超过 1000 条时，需要扩展分页加载逻辑。
|
||||
- 服务端加密参数变化时，需要同步修改 `src/CryptoUtils.cpp`。
|
||||
- 发布桌面版本时，使用 Qt 部署工具收集运行时依赖。
|
||||
- 发布 Android 版本时，建议补充签名配置和 release 构建流程。
|
||||
- 如果需要修改历史提交作者，请在推送前完成，避免远程协作历史冲突。
|
||||
|
||||
## 开源协议
|
||||
|
||||
本项目采用 MIT License 开源，详见 `LICENSE` 文件。
|
||||
@@ -0,0 +1,2 @@
|
||||
android.overridePathCheck=true
|
||||
android.useAndroidX=true
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 8.8 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 4.6 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 14 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 27 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 44 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 20 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 627 B |
Binary file not shown.
|
After Width: | Height: | Size: 39 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 67 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 1.8 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 3.7 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 6.0 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 99 KiB |
@@ -0,0 +1 @@
|
||||
IDI_ICON1 ICON "@REWRITE_QT_APP_ICON@"
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user